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NAND Flash Memory
MT29F16G08CBABA, MT29F16G08CBABB
Features
•
Open NAND Flash Interface (ONFI) 2.1-compliant
1
•
Multiple-level cell (MLC) technology
•
Organization
–
Page size x8: 4320 bytes (4096 + 224 bytes)
–
Block size: 256 pages (1024K + 56K bytes)
–
Plane size: 2 planes x 1024 blocks per plane
–
Device size: 16Gb: 2048 blocks
•
Synchronous I/O performance
–
Up to synchronous timing mode 4
–
Clock rate: 12ns (DDR)
–
Read/write throughput per pin: 166 MT/s
•
Asynchronous I/O performance
–
Up to asynchronous timing mode 4
–
t
RC/
t
WC: 25ns (MIN)
•
Array performance
–
Read page: 50µs (MAX)
–
Program page: 900µs (TYP)
–
Erase block: 3ms (TYP)
•
Operating Voltage Range
–
Vcc: 2.7–3.6V
–
Vccq: 1.7–1.95V, 2.7–3.6V
•
Command set: ONFI NAND Flash Protocol
•
Advanced Command Set
–
Program cache
–
Read cache sequential
–
Read cache random
–
One-time programmable (OTP) mode
–
Multi-plane commands
–
Multi-LUN operations
–
Read unique ID
–
Copyback
•
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 93).
•
RESET (FFh) required as first command after power-
on
•
Operation status byte provides software method for
detecting
–
Operation completion
–
Pass/fail condition
–
Write-protect status
•
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data I/O in the synchronous
interface
•
Copyback operations supported within the plane
from which data is read
•
Quality and reliability
–
Data retention: 10 years
–
Endurance: 5,000 PROGRAM/ERASE cycles
•
Operating temperature:
–
Commercial: 0°C to +70°C
–
Industrial (IT): –40ºC to +85ºC
•
Package
–
52-pad LGA
–
48-pin TSOP
Note:
1. The ONFI 2.1 specification is available at
www.onfi.org.
Micron Confidential and Proprietary
16Gb Asynchronous/Synchronous NAND Flash Memory
Features
PDF: 09005aef836c9e38
Rev. F 01/10 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 16G 08 C B A B A WP ES :B
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
16G = 16Gb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B 1 1 1 Common
Operating Voltage Range
A = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 3.3V (2.7–3.6V)
Generation Feature Set
B = Second set of device features
Interface
A = Async only
B = Sync / Async
Design Revision
B = Second revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Extended (–40°C to +85°C)
Speed Grade (synchronous mode only)
-12 = 166 MT/s
Package Code
C3 = 52-pad ULGA 12mm x 17mm x 0.65mm
1
WP = 48-pin TSOP
1
(CPL)
Note:
1. Pb-free package.
Micron Confidential and Proprietary
16Gb Asynchronous/Synchronous NAND Flash Memory
Features
PDF: 09005aef836c9e38
Rev. F 01/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 13
Architecture ................................................................................................................................................... 15
Device and Array Organization ....................................................................................................................... 16
Bus Operation – Asynchronous Interface ........................................................................................................ 18
Asynchronous Enable/Standby ................................................................................................................... 18
Asynchronous Bus Idle ............................................................................................................................... 18
Asynchronous Commands .......................................................................................................................... 19
Asynchronous Addresses ............................................................................................................................ 20
Asynchronous Data Input ........................................................................................................................... 21
Asynchronous Data Output ........................................................................................................................ 22
Write Protect .............................................................................................................................................. 23
Ready/Busy# .............................................................................................................................................. 23
Bus Operation – Synchronous Interface ........................................................................................................... 28
Synchronous Enable/Standby ..................................................................................................................... 29
Synchronous Bus Idle/Driving .................................................................................................................... 29
Synchronous Commands ........................................................................................................................... 30
Synchronous Addresses .............................................................................................................................. 31
Synchronous DDR Data Input ..................................................................................................................... 32
Synchronous DDR Data Output .................................................................................................................. 33
Write Protect .............................................................................................................................................. 35
Ready/Busy# .............................................................................................................................................. 35
Device Initialization ....................................................................................................................................... 36
Activating Interfaces ....................................................................................................................................... 37
Activating the Asynchronous Interface ........................................................................................................ 37
Activating the Synchronous Interface .......................................................................................................... 37
Command Definitions .................................................................................................................................... 39
Reset Operations ............................................................................................................................................ 41
RESET (FFh) ............................................................................................................................................... 41
SYNCHRONOUS RESET (FCh) .................................................................................................................... 42
Identification Operations ................................................................................................................................ 43
READ ID (90h) ............................................................................................................................................ 43
READ ID Parameter Tables ............................................................................................................................. 44
READ PARAMETER PAGE (ECh) ...................................................................................................................... 45
Parameter Page Data Structure Tables ............................................................................................................. 46
READ UNIQUE ID (EDh) ................................................................................................................................ 51
Configuration Operations ............................................................................................................................... 52
SET FEATURES (EFh) ................................................................................................................................. 52
GET FEATURES (EEh) ................................................................................................................................. 53
Status Operations ........................................................................................................................................... 57
READ STATUS (70h) ................................................................................................................................... 58
READ STATUS ENHANCED (78h) ............................................................................................................... 59
Column Address Operations ........................................................................................................................... 60
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 60
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 61
CHANGE WRITE COLUMN (85h) ................................................................................................................ 62
CHANGE ROW ADDRESS (85h) ................................................................................................................... 63
Read Operations ............................................................................................................................................. 65
Micron Confidential and Proprietary
16Gb Asynchronous/Synchronous NAND Flash Memory
PDF: 09005aef836c9e38
Rev. F 01/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
READ MODE (00h) ..................................................................................................................................... 67
READ PAGE (00h-30h) ................................................................................................................................ 68
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 69
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 70
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 72
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 73
Program Operations ....................................................................................................................................... 75
PROGRAM PAGE (80h-10h) ........................................................................................................................ 75
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 77
PROGRAM PAGE MULTI-PLANE 80h-11h ................................................................................................... 79
Erase Operations ............................................................................................................................................ 81
ERASE BLOCK (60h-D0h) ............................................................................................................................ 81
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 82
Copyback Operations ..................................................................................................................................... 83
COPYBACK READ (00h-35h) ....................................................................................................................... 84
COPYBACK PROGRAM (85h–10h) ............................................................................................................... 85
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 85
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ........................................................................................ 86
One-Time Programmable (OTP) Operations .................................................................................................... 87
PROGRAM OTP PAGE (80h-10h) ................................................................................................................. 88
PROTECT OTP AREA (80h-10h) ................................................................................................................... 89
READ OTP PAGE (00h-30h) ......................................................................................................................... 90
Multi-Plane Operations .................................................................................................................................. 91
Multi-Plane Addressing .............................................................................................................................. 91
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 92
Error Management ......................................................................................................................................... 93
Output Drive Impedance ................................................................................................................................ 94
AC Overshoot/Undershoot Specifications ....................................................................................................... 97
Synchronous Input Slew Rate ......................................................................................................................... 98
Output Slew Rate ............................................................................................................................................ 99
Electrical Specifications ................................................................................................................................. 100
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 102
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 102
Electrical Specifications – DC Characteristics and Operating Conditions (V
CCQ
) ............................................... 103
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 103
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 106
Electrical Specifications – Array Characteristics .............................................................................................. 109
Asynchronous Interface Timing Diagrams ...................................................................................................... 110
Synchronous Interface Timing Diagrams ........................................................................................................ 121
Revision History ............................................................................................................................................ 143
Rev. F Production – 1/10 ............................................................................................................................ 143
Rev. E – 8/09 .............................................................................................................................................. 143
Rev. D – 2/09 ............................................................................................................................................. 143
Rev. C – 1/09 ............................................................................................................................................. 143
Rev. B – 12/08 ............................................................................................................................................ 144
Rev. A – 11/08 ............................................................................................................................................ 145
Micron Confidential and Proprietary
16Gb Asynchronous/Synchronous NAND Flash Memory
PDF: 09005aef836c9e38
Rev. F 01/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 17
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 18
Table 4: Synchronous Interface Mode Selection ............................................................................................. 28
Table 5: Command Set .................................................................................................................................. 39
Table 6: Read ID Parameters for Address 00h ................................................................................................. 44
Table 7: Read ID Parameters for Address 20h .................................................................................................. 44
Table 8: Parameter Page Data Structure ......................................................................................................... 46
Table 9: Feature Address Definitions .............................................................................................................. 52
Table 10: Feature Address 01h: Timing Mode ................................................................................................. 54
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 54
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 55
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 55
Table 14: Status Register Definition ............................................................................................................... 57
Table 15: OTP Area Details ............................................................................................................................ 88
Table 16: Error Management Details .............................................................................................................. 93
Table 17: Output Drive Strength Test Conditions (V
CCQ
= 1.7–1.95V) ............................................................... 94
Table 18: Output Drive Strength Impedance Values (V
CCQ
= 1.7–1.95V) ........................................................... 94
Table 19: Output Drive Strength Conditions (V
CCQ
= 2.7–3.6V) ........................................................................ 95
Table 20: Output Drive Strength Impedance Values (V
CCQ
= 2.7–3.6V) ............................................................. 95
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 96
Table 22: Overshoot/Undershoot Parameters ................................................................................................. 97
Table 23: Test Conditions for Input Slew Rate ................................................................................................. 98
Table 24: Input Slew Rate (V
CCQ
= 2.7–3.6V) .................................................................................................... 98
Table 25: Test Conditions for Output Slew Rate .............................................................................................. 99
Table 26: Output Slew Rate (V
CCQ
= 1.7–1.95V) ............................................................................................... 99
Table 27: Output Slew Rate (V
CCQ
= 2.7–3.6V) ................................................................................................. 99
Table 28: Absolute Maximum Ratings by Device ............................................................................................ 100
Table 29: Recommended Operating Conditions ............................................................................................ 100
Table 30: Valid Blocks per LUN ..................................................................................................................... 100
Table 31: Capacitance: 48-Pin TSOP Package ................................................................................................ 100
Table 32: Pad Capacitance: 52-Pad LGA Package ........................................................................................... 101
Table 33: Test Conditions ............................................................................................................................. 102
Table 34: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 102
Table 35: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 102
Table 36: DC Characteristics and Operating Conditions (3.3V V
CCQ
) ............................................................... 103
Table 37: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 103
Table 38: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 106
Table 39: Array Characteristics ..................................................................................................................... 109
Micron Confidential and Proprietary
16Gb Asynchronous/Synchronous NAND Flash Memory
PDF: 09005aef836c9e38
Rev. F 01/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
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