SATA 3.0协议详解：高速串行数据连接

SATA

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"SATA 3.0协议标准" SATA（Serial Advanced Technology Attachment）是一种高速接口标准，用于连接计算机系统和存储设备，如硬盘驱动器、光驱等。SATA 3.0是该标准的一个重要版本，它在2009年被Serial ATA International Organization（SATA-IO）发布，并被誉为“Gold Revision”。这个版本显著提高了数据传输速度和性能，旨在满足不断增长的存储需求。 SATA 3.0协议标准的主要改进包括： 1. **传输速率提升**：SATA 3.0将最大数据传输率提升到了6Gbps（600MB/s），相比SATA 2.0的3Gbps翻了一倍。这得益于新的8b/10b编码方案，它在保持信号完整性的前提下提高了数据传输效率。 2. **Power Management优化**：SATA 3.0引入了更高级的电源管理功能，如AHCI（Advanced Host Controller Interface）的SMART（Self-Monitoring, Analysis, and Reporting Technology）和APM（Advanced Power Management）特性，允许设备在不使用时进入低功耗模式，从而节省能源。 3. **PHY Link Transport层**：这部分是SATA协议的核心，负责物理层的数据传输。SATA 3.0在这一层做了很多工作，确保在高数据速率下的信号质量和稳定性。它包括了错误检测与校正机制，如CRC（Cyclic Redundancy Check）和ECC（Error Correction Code），以及对噪声和干扰的抵抗能力增强。 4. **异常处理**：SATA 3.0在协议层面上增加了对各种异常情况的处理，如数据包丢失、时钟同步问题、链路故障等。这些增强的错误恢复机制有助于保持数据的完整性，同时减少了因硬件问题导致的系统停机时间。 5. **兼容性**：尽管SATA 3.0提高了传输速度，但它仍保持向下兼容，能够与较早的SATA 2.0和1.0设备正常工作，只是速度会受到限制。 6. **NCQ（Native Command Queuing）优化**：SATA 3.0进一步提升了NCQ的性能，这是一种允许硬盘驱动器内部优化命令执行顺序的技术，以减少读写操作的延迟。 7. **热插拔支持**：SATA 3.0继续支持热插拔功能，用户可以在系统运行时安全地添加或移除SATA设备，而不会造成数据丢失或系统崩溃。 SATA 3.0协议标准通过提高传输速率、优化电源管理和错误处理，以及增强兼容性和性能特性，为用户提供了更快、更稳定、更节能的存储解决方案。在现代计算机系统中，SATA 3.0接口广泛应用于桌面、笔记本电脑及服务器，为各种存储应用提供高效、可靠的连接。

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Serial ATA Revision 3.0 Gold Revision page 16 of 663

Figure 161 – Receiver Jitter and CM Tolerance Test – Setting TJ and CM Levels (Gen3i) ....... 294

Figure 162 – Receiver Jitter and CM Tolerance Test (Gen3i) .................................................... 294

Figure 163 – Return Loss Test-Calibration ................................................................................. 295

Figure 164 – Return Loss Test .................................................................................................... 297

Figure 165 – Intra-Pair Skew Test for a Transmitter ................................................................... 299

Figure 166 – Receiver Intra-Pair Skew Test—Setting Levels ..................................................... 299

Figure 167 – Receiver Intra-Pair Skew Test ............................................................................... 299

Figure 168 – Example Intra-Pair Skew test for Transmitter (10.8 pS) ........................................ 300

Figure 169 – TX/RX Sequencing Transient Voltage Measurement ............................................ 300

Figure 170 – AC Coupled Capacitance Measurement................................................................ 301

Figure 171 – Squelch Detector Threshold Test—Setting Levels ................................................ 303

Figure 172 – Squelch Detector Threshold Test........................................................................... 304

Figure 173 – TDR Differential Impedance Test—Setting Risetime............................................. 306

Figure 174 – TDR Impedance Test ............................................................................................. 306

Figure 175 – TDR Single-Ended Impedance Test—Setting Risetime ........................................ 307

Figure 176 – DC Coupled Common Mode Voltage Measurement.............................................. 307

Figure 177 – AC Coupled Common Mode Voltage Measurement.............................................. 308

Figure 178 – TDR Impedance Test ............................................................................................. 308

Figure 179 - Sequencing Transient Voltage Laboratory Load .................................................... 309

Figure 180 – OOB Signals........................................................................................................... 310

Figure 181 – Transmitter Examples ............................................................................................ 311

Figure 182 – Transmitter Examples (Concluded)........................................................................ 312

Figure 183 – COMRESET Sequence.......................................................................................... 313

Figure 184 – COMINIT Sequence ............................................................................................... 314

Figure 185 – OOB Signal Detector.............................................................................................. 316

Figure 186 – Squelch Detector.................................................................................................... 317

Figure 187 – Power-On Sequence.............................................................................................. 330

Figure 188 – PHYRDY to Partial—Host Initiated ........................................................................ 332

Figure 189 – PHYRDY to Partial—Device Initiated..................................................................... 333

Figure 190 – Nomenclature Reference ....................................................................................... 336

Figure 191 – Bit Ordering and Significance................................................................................. 346

Figure 192 – Transmission Structures ........................................................................................ 348

Figure 193 – FIS type value assignments ................................................................................... 383

Figure 194 – Register - Host to Device FIS layout ...................................................................... 384

Figure 195 – Register - Device to Host FIS layout ...................................................................... 386

Figure 196 – Set Device Bits - Device to Host FIS layout ........................................................... 387

Figure 197 – DMA Activate - Device to Host FIS layout.............................................................. 388

Figure 198 – DMA Setup – Device to Host or Host to Device FIS layout ................................... 389

Figure 199 – BIST Activate - Bidirectional................................................................................... 392

Figure 200 – PIO Setup - Device to Host FIS layout................................................................... 395

Figure 201 – Data – Host to Device or Device to Host FIS layout .............................................. 397

Figure 202 –DEVICE CONFIGURATION IDENTIFY data structure ........................................... 494

Figure 203 - DEVICE CONFIGURATION SET data structure .................................................... 495

Figure 204 – DMA Setup FIS definition for memory buffer selection .......................................... 501

Figure 205 – READ FPDMA QUEUED command definition....................................................... 504

Figure 206 – READ FPDMA QUEUED error on command receipt............................................. 506

Figure 207 - Set Device Bits FIS with error notification, and command completions ................. 507

Figure 208 - Set Device Bits FIS aborting all outstanding command.......................................... 508

Figure 209 – WRITE FPDMA QUEUED command definition ..................................................... 509

Figure 210 - Set Device Bits FIS for successful WRITE FPDMA QUEUED command completion

............................................................................................................................................. 510

Figure 211 – WRITE FPDMA QUEUED error on command receipt ........................................... 511

Figure 212 - Set Device Bits FIS with error notification, and command completions ................. 512

Figure 213 - NCQ QUEUE MANAGEMENT - Command definition ........................................... 513

Figure 214 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - Successful completion........ 515

Figure 215 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - error on command receipt .. 516

Serial ATA Revision 3.0 Gold Revision page 17 of 663

Figure 216 - NCQ QUEUE MANAGEMENT, Abort NCQ Queue – error during execution......... 517

Figure 217 – NCQ QUEUE MANAGEMENT, Deadline Handling - Successful completion........ 520

Figure 218 – NCQ QUEUE MANAGEMENT, Deadline Handling - error on command receipt .. 520

Figure 219 - NCQ QUEUE MANAGEMENT, Deadline Handling – error during execution......... 521

Figure 220 – Example DMA engine indirection for First-party DMA support .............................. 522

Figure 221 – Queued Error Log data structure definition ............................................................ 525

Figure 222 – NCQ Queue Management Log (12h) data structure definition .............................. 527

Figure 223 – Phy Event Counter Identifiers ................................................................................ 530

Figure 224 – Phy Event Counters Log data structure definition.................................................. 532

Figure 225 – Generic enclosure services topology ..................................................................... 537

Figure 226 – Simplified view of generic topology ........................................................................ 537

Figure 227 – Enclosure services definition configuration ............................................................ 538

Figure 228 – Register Signature Indicating Presence of Enclosure Services Device................. 539

Figure 229 – Register Signature for Absent Enclosure Processor.............................................. 539

Figure 230 – Command Block Register Fields Used in Enclosure Processor Communications 540

Figure 231 – I

C Frame for Conveying an Enclosure Services Command ................................. 541

Figure 232 – WRITE SEP Command Block Registers................................................................ 542

Figure 233 – I

C Transactions Corresponding to a WRITE SEP Command .............................. 543

Figure 234 – READ SEP Command Block Registers ................................................................. 544

Figure 235 – I

C Transactions Corresponding to READ SEP Command ................................... 544

Figure 236 – IDENTIFY SEP data structure definition ................................................................ 545

Figure 237 – SAF-TE Write Device Slot Status data structure ................................................... 547

Figure 238 – SES Device Element data structure....................................................................... 548

Figure 239 – Example Subsystem............................................................................................... 549

Figure 240 – SAF-TE Device ID field convention........................................................................ 549

Figure 241 – SES Slot Address field convention......................................................................... 550

Figure 242 – Activity LED definition for desktop behavior emulation.......................................... 552

Figure 243 – Device Activity LEDs with Separate Wires............................................................. 553

Figure 244 – Device Activity LEDs with Ribbon Cable................................................................ 554

Figure 245 – Device Activity LEDs in a Storage Subsystem....................................................... 555

Figure 246 – Software reset to control port result values............................................................ 556

Figure 247 – Port Multiplier Signature......................................................................................... 558

Figure 248 – SActive register definition....................................................................................... 565

Figure 249 – SNotification register definition............................................................................... 565

Figure 250 – Error handling architecture..................................................................................... 567

Figure 251 – Port Multiplier Overview ......................................................................................... 577

Figure 252 – Port Selector Overview........................................................................................... 607

Figure 253 – Example Failover Application with Two Hosts ....................................................... 608

Figure 254 – Port selection signal based on assertion of COMRESET to assertion of following

COMRESET ........................................................................................................................ 610

Figure 255 – Complete port selection signal consisting of two sequences with requisite inter-reset

spacings............................................................................................................................... 611

Figure 256 – Control State Machine............................................................................................ 613

Figure 257 – Phy Block Diagram................................................................................................. 614

Figure 258 – Concept summary interconnect structure .............................................................. 644

Figure 259 – An example of signal connections with one I/O Controller..................................... 645

Figure 260 – Example of signal connections with two I/O Modules ............................................ 647

Figure 261 – High Speed Channels – Configuration 0................................................................ 648

Figure 262 – High-Speed Channels – Configuration 1 ............................................................... 648

Figure 263 – Low Speed Channels ............................................................................................. 649

Figure 264 – Interconnect Channels ........................................................................................... 649

Figure 265 – I/O Controller Module Connector Rendering.......................................................... 650

Figure 266 – Connector Pin Layout and Pin Lengths.................................................................. 651

Figure 267 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 652

Figure 268 – Side View of Connector.......................................................................................... 652

Figure 269 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 654

Serial ATA Revision 3.0 Gold Revision page 19 of 663

LIST OF TABLES

Table 1 – State Table Cell Description.......................................................................................... 44

able 2 – Usage Model Descriptions............................................................................................. 50

Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 82

Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 91

Table 5 – Housing and contact electrical parameters, test procedures, and requirements.......... 95

Table 6 – Mechanical test procedures and requirements ............................................................. 96

Table 7 – Environmental parameters, test procedures, and requirements ................................... 97

Table 8 – Additional requirement................................................................................................... 97

Table 9 – Connector test sequences............................................................................................. 98

Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence............. 119

Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 119

Table 12 – Slimline Connector Location References .................................................................. 122

Table 13 – Slimline Device plug connector pin definition ............................................................ 131

Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 138

Table 15 - Signal and Power Internal LIF-SATA Plug ................................................................. 145

Table 16 - Unique Connector Mechanical Testing Procedures and Requirements .................... 146

Table 17 – Multilane Pin Assignments ........................................................................................ 161

Table 18 – Internal Cable / Connector Measurement Parameter and Requirements................. 165

Table 19 – External Single Lane Cable / Connector Measurement Parameter and Requirements

............................................................................................................................................. 165

Table 20 – Limited External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 166

Table 21 – Extended External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 166

Table 22 – Common Interconnect Measurement Procedure Methodologies.............................. 169

Table 23 – Interconnect Test Methodologies / Procedures......................................................... 170

Table 24 – Power segment pin P11 activity signal electrical parameters ................................... 176

Table 25 – Host activity signal electrical parameters .................................................................. 176

Table 26 – Activity signal functional states.................................................................................. 177

Table 27 – Host staggered spin-up control electrical requirements ............................................ 178

Table 28 – Comparator voltages for alternate example presence detection circuit .................... 181

Table 29 – General Specifications............................................................................................... 193

Table 30 – Transmitter Specifications ......................................................................................... 195

Table 31 – Transmitted Signal Requirements ............................................................................. 198

Table 32 – Receiver Specifications ............................................................................................. 202

Table 33 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 206

Table 34 – OOB Specifications ................................................................................................... 209

Table 35 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 233

Table 36 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 234

Table 37 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 235

Table 38 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 236

Table 39 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 237

Table 40 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+ ..................... 238

Table 41 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 239

Table 42 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 239

Table 43 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 240

Table 44 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 240

Table 45 – Composite-Bit Pattern (COMP) Starting with RD–.................................................... 241

Table 46 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 244

Table 47 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 262

Table 48 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 264

Table 49 – OOB Signal Times..................................................................................................... 310

Table 50 – Interface Power States .............................................................................................. 319

Serial ATA Revision 3.0 Gold Revision page 20 of 663

Table 51 – State Diagram Host Phy Initialization State Machine................................................ 321

Table 52 – State Diagram Device Phy Initialization State Machine ............................................ 325

Table 53 – Bit Designations......................................................................................................... 336

Table 54 – Conversion Examples................................................................................................ 337

Table 55 – 5B/6B Coding ............................................................................................................ 339

Table 56 – 3B/4B Coding ............................................................................................................ 339

Table 57 – Encoding Examples................................................................................................... 340

Table 58 – Valid Data Characters ............................................................................................... 341

Table 59 – Valid Control Characters ........................................................................................... 345

Table 60 – Single Bit Error with Two Character Delay ................................................................ 347

Table 61 – Single Bit Error with One Character Delay ................................................................ 347

Table 62 – Description of Primitives............................................................................................ 349

Table 63 – Primitive Encoding..................................................................................................... 350

Table 64 – CONT

Usage Example ............................................................................................ 352

Table 65 – Example of Components of a Round Trip Delay....................................................... 355

Table 66 – SRST Write from Host to Device Transmission Breaking Through a Device to Host

Data FIS............................................................................................................................... 356

Table 67 – Command Shadow Register Block Register Transmission Example ....................... 356

Table 68 – Data from Host to Device Transmission Example..................................................... 357

Table 69 – State Diagram Link Idle ............................................................................................. 360

Table 70 – State Diagram Link Transmit..................................................................................... 363

Table 71 – State Diagram Link Receive...................................................................................... 370

Table 72 – State Diagram Link Power Mode............................................................................... 376

Table 73 – Simplified Shadow Register Block register numbering ............................................. 382

Table 74 – BIST Activate FIS Modes and Bit Settings ................................................................ 393

Table 75 – IDENTIFY DEVICE information................................................................................. 479

Table 76 - Coded Values for Negotiated Serial ATA Signaling Speed ....................................... 484

Table 77 – IDENTIFY PACKET DEVICE information ................................................................. 487

Table 78 - Features enable/disable values ................................................................................. 492

Table 79 - Feature identification values ...................................................................................... 492

Table 80 - Subcommand Field .................................................................................................... 513

Table 81 - Abort Type.................................................................................................................. 515

Table 82- Log Addresses for Serial ATA..................................................................................... 523

Table 83 - General Purpose Log directory values for Serial ATA ............................................... 524

Table 84 – SCR definition............................................................................................................ 560

Table 85 – SCR Definition ........................................................................................................... 560

Table 86 – State Diagram Collisions ........................................................................................... 581

Table 87 – State Diagram Hot Plug State Machine for Host Port ............................................... 583

Table 88 – State Diagram Hot Plug State Machine for Device Port............................................ 585

Table 89 – Register Values for an Unsupported Command ....................................................... 588

Table 90 – Static Information Registers ...................................................................................... 590

Table 91 – Status Information and Control Registers ................................................................. 592

Table 92 – Features Supported Registers .................................................................................. 596

Table 93 – Features Enabled Registers ...................................................................................... 597

Table 94 – Vendor Unique Registers .......................................................................................... 598

Table 95 – Phy Event Counter Registers .................................................................................... 599

Table 96 – Reserved Registers ................................................................................................... 599

Table 97 – PSCR Definition......................................................................................................... 600

Table 98 – READ PORT MULTIPLIER Command Definition ..................................................... 600

Table 99 – READ PORT MULTIPLIER Success Status Result Values ...................................... 601

Table 100 – READ PORT MULTIPLIER Error Status Result Values.......................................... 602

Table 101 – WRITE PORT MULTIPLIER Command Definition.................................................. 602

Table 102 – WRITE PORT MULTIPLIER Success Status Result Values .................................. 603

Table 103 – WRITE PORT MULTIPLIER Error Status Result Values ........................................ 604

Table 104 – Port selection signal inter-reset timing requirements .............................................. 610

Table 105 – CRC and scrambler calculation example - PIO Write Command ........................... 630

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