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MCIMX27RM
Rev. 0.2
9/2007
MCIMX27 Multimedia
Applications Processor
Reference Manual
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including “Typicals”, must be validated for each customer application by customer’s technical experts.
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MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor iii
Contents
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx
Chapter 1
Introduction to the i.MX27 Multimedia Applications Processor
1.1 i.MX27 Applications Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Summary of Core and Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 ARM9™ Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.3 Standard System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.4 Power Management and Backup Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.5 System Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.6 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2.7 Wireline Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.8 External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.9 Memory Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.2.10 Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt) . . . . . . . . . . . . . . . 1-17
1.2.11 MultiMedia Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
1.2.12 Human Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
1.2.13 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Chapter 2
System Memory and Register Map
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2.1 Detailed Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Chapter 3
Clocks, Power Management, and Reset Control
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Clock Controller Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2.1 High Frequency Clock Source and Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Output Frequency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.1 PLL Operation at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.2 PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
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MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
iv Freescale Semiconductor
3.3.3 i.MX27 Processor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.4 SDRAM Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.3.5 Power Management in the PLL Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.3.6 Power Management Using Frequency Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.2 Clock Source Control Register (CSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.3 MPLL Control Register 0 (MPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4.4 MCU and System PLL Control Register 1 (MPCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.4.5 Programming the Serial Peripheral PLL (SPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.6 SPLL Control Register 0 (SPCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.7 SPLL Control Register 1 (SPCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.8 Oscillator 26M Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.4.9 Peripheral Clock Divider Register 0 (PCDR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.4.10 Peripheral Clock Divider Register 1 (PCDR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.11 Peripheral Clock Control Register 0 (PCCR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4.12 Peripheral Clock Control Register 1 (PCCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.4.13 Clock Control Status Register (CCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.4.14 Wakeup Guard Mode Control Register (WKGDCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.5 Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.1 Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.5.2 ARM9 Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Chapter 4
System Control
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2.1 Chip ID Register (CID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2 Function Multiplexing Control Register (FMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 Global Peripheral Control Register (GPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.4 Well Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.5 Well Bias Control Register (WBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.6 Drive Strength Control Register 1 (DSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.2.7 Drive Strength Control Register 2 (DSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.2.8 Drive Strength Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.2.9 Drive Strength Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.2.10 Drive Strength Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.2.11 Drive Strength Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.2.12 Drive Strength Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.2.13 Drive Strength Control Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4.2.14 Drive Strength Control Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.2.15 Drive Strength Control Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.2.16 Drive Strength Control Register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.2.17 Drive Strength Control Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
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MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor v
4.2.18 Drive Strength Control Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.2.19 Pull Strength Control Register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4.2.20 Priority Control and Select Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
4.2.21 Power Management Control Register (PMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
4.2.22 DPTC Comparator Value Register 0 (DCVR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.2.23 DPTC Comparator Value Register 1 (DCVR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.2.24 DPTC Comparator Value Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
4.2.25 DPTC Comparator Value Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
4.2.26 PMIC Pad Control Register (PPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
4.3 System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Chapter 5
Signal Descriptions and Pin Assignments
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 I/O Power Supply and Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.1 Pull/Pull Strength/Open Drain Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3.2 GPIO Default and Pull-Up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3.3 I/O Mode and Supply Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Chapter 6
General-Purpose I/O (GPIO)
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 GPIO Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.4 External Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.6 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.6.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.6.2 Data Direction Register (PTn_DDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.3 Output Configuration Register 1 (OCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.4 Output Configuration Register 2 (OCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.6.5 Input Configuration Register A1 (ICONFA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.6.6 Input Configuration Register A2 (ICONFA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.6.7 Input Configuration Register B1 (ICONFB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.6.8 Input Configuration Register B2 (ICONFB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6.9 Data Register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.6.10 GPIO IN USE Registers (GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.6.11 GPIO IN USE Register Reset Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.6.12 Sample Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.6.13 Interrupt Configuration Register 1 (ICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.6.14 Interrupt Configuration Register 2 (ICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.6.15 Interrupt Mask Register (IMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
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