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The Virtex®-6 FPGA SelectIO™ technology can perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path. The ISERDESE1 is located in the SelectIO logic block and contains four phases of dedicated flip-flops used for sampling. The MMCM is an advanced PLL that has the capability to provide a phase-shifted clock on a low-jitter performance path.
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XAPP881 (v1.0.1) July 25, 2010 www.xilinx.com 1
© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Summary The Virtex®-6 FPGA SelectIO™ technology can perform 4X asynchronous oversampling at
1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the
mixed-mode clock manager (MMCM) dedicated performance path. The ISERDESE1 is located
in the SelectIO logic block and contains four phases of dedicated flip-flops used for sampling.
The MMCM is an advanced PLL that has the capability to provide a phase-shifted clock on a
low-jitter performance path.
The output of the ISERDESE1 is then sorted using a data recovery unit (DRU). The DRU used
in this application note is based on a voter system that compares the outputs and selects the
best data sample.
Asynchronous
Oversampling
Overview
The most common way of sending data from one device to another is to send synchronized
clock and data together. This approach is known as source-synchronous data. When data is
sent without a clock, it is known as asynchronous data.
An asynchronous data capture scheme is the focus of this application note. The method used
consists of oversampling the data with a clock of similar frequency (±100 ppm). This
oversampling technique involves taking multiple samples of the data at different clock phases to
get a sample of the data at the most ideal point. Figure 1 is a basic diagram of 4X
asynchronous oversampling.
Application Note: Virtex-6 FPGAs
XAPP881 (v1.0.1) July 25, 2010
Virtex-6 FPGA LVDS 4X Asynchronous
Oversampling at 1.25 Gb/s
Authors: Catalin Baetoniu and Brandon Day
X-Ref Target - Figure 1
Figure 1: Basic Architecture and Conceptual View of 4X Oversampling
125 MHz ±100 ppm
125 MHz ±100 ppm
625 MHz
8
x881_01_062410
Data at 1.25 Gb/s
Transmitter
Capture
Clock
Multiplier
Data
Recovery
![](https://csdnimg.cn/release/download_crawler_static/4277346/bg2.jpg)
Asynchronous Oversampling Overview
XAPP881 (v1.0.1) July 25, 2010 www.xilinx.com 2
Figure 1 shows some of the key elements of the 4X oversampling technique. The transmitted
data is generated using an oscillator with a particular frequency and drift, and the data is then
captured using an independent, asynchronous oscillator. An inherent challenge in such a
scenario is the frequency drift differential between the sending and receiving oscillators, which
must be taken into account when performing data capture across clock domains. The data
sampled is then processed in the data recovery portion of the receiver using a voter system.
Figure 2 shows the sampling clock running at one-half the rate of the data. With the clock phase
sample points shown, this produces eight samples of data coming out of the capture block: four
for the rising-edge data and four for the falling-edge data.
X-Ref Target - Figure 2
Figure 2: Phase of Sampling Clocks for Rising and Falling Edge Data
0 45 90 135 180 225 270 315
X881_02_050610
Rising Data Falling Data
![](https://csdnimg.cn/release/download_crawler_static/4277346/bg3.jpg)
Virtex-6 FPGA Oversampling Architecture
XAPP881 (v1.0.1) July 25, 2010 www.xilinx.com 3
Virtex-6 FPGA
Oversampling
Architecture
The Virtex-6 FPGA method of creating four samples per bit has advantages over the methods
used previously, where flip-flops in the CLB arrays were used to create multiple samples. The
sampling flip-flops are moved from the CLB to inside the ISERDESE1, as shown in Figure 3.
The staged sampling inside the ISERDESE1 is to counter any metastability issues. This also
allows all of the data to come out of the ISERDESE1 on one clock domain.
The ISERDESE1 in oversampling mode is essentially a dual set of DDR flip-flops, as shown in
Figure 4. The IODELAYE1 is used to create a phase-shifted version of the data on the slave
side of the ISERDESE1 that can be sampled along with the unshifted original version.
X-Ref Target - Figure 3
Figure 3: View of ISERDESE1 Primitive in Oversample Mode
DDLY CLK
CLK
OCLK
OCLK
Q5
Q6
Q4
Q3
Q2
Q1
SHIFTOUT 1
SHIFTOUT 2
O
CLK
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
CLK
REG
DQ
x881_03_070710
CLK
REG
DQ
CLK
REG
DQ
CLKB
CE2
CE1
OCLK
CLKDIV
DYNCLKSEL
DYNCLKDIVSEL
SHIFTIN 1
SHIFTIN 2
RST
D
BITSLIP
OFB
ISERDESE1 Primitive
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