musbmhdrc_pspgUSB控制器芯片手册.pdf

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MENTOR

GRAPHICS

THE INTELLIGENT APPROACH TO INTELLECTUAL PROPERTY

CONFIDENTIAL

BUS INTERFACE

MUSBMHDRC

USB 2.0 MULTI-POINT

DUAL-ROLE CONTROLLER

Product Specification

and Programming Guide

SBMHDRC PRODUCT

CONFIDENTIAL

MUSBMHDRC

Confidential. May be photocopied by licensed customers of Mentor Graphics for internal business purposes only.

The product(s) described in this document are trade secret and proprietary products of Mentor Graphics Corporation or its

licensors and are subject to license terms. No part of this document may be photocopied, reproduced or translated, disclosed

or otherwise provided to third parties, without the prior written consent of Mentor Graphics.

The document is for informational and instructional purposes. Mentor Graphics reserves the right to make changes in

specifications and other information contained in this publication without prior notice, and the reader should, in all cases,

consult Mentor Graphics to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in the written contracts

between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be

deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT

LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL

DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO

THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS

BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in the

subdivision (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

A complete list of trademark names appears in a separate “Trademark Information” document.

Mentor Graphics Corporation

8005 S.W. Boeckman Road, Wilsonville, Oregon 97070.

This is an unpublished work of Mentor Graphics Corporation.

For Customer Support on this product:

• Call up the Customer Inquiry Service at http://www.mentor.com/supportnet

• Email support_net@mentor.com

• Phone 1-800-547-4303 (toll-free in US, Mexico and Canada)

(Customers in other parts of the world should contact their local Mentor Graphics support office.)

Full details are given in the Customer Support Handbook, provided in Adobe Acrobat format as custhb.pdf in the

/databook directory on Mentor Graphics Soft Cores CDs. Please note the checklists of actions to take and

information to have to hand when contacting Customer Support that are given in the Customer Support Handbook.

CONTENTS CONFIDENTIAL

MUSBMHDRC PRODUCT SPECIFICATION

AND PROGRAMMER’S GUIDE

TABLE OF CONTENTS

1. INTRODUCTION ................................................................................................... 11

2. FUNCTIONAL DESCRIPTION .......................................................................... 13

2.1. Modes of Operation.................................................................................................. 13

2.2. Block Diagram............................................................................................................ 14

2.3. UTM Synchronization ............................................................................................... 14

2.4. Packet Encoding/Decoding ..................................................................................... 15

2.5. Endpoint Controllers................................................................................................. 15

2.6. CPU Interface............................................................................................................. 15

2.7. RAM Controller ......................................................................................................... 15

2.8. DMA Controller Support.......................................................................................... 15

2.9. Tree Diagram .............................................................................................................. 16

3. REGISTER DESCRIPTION.................................................................................. 23

3.1. MUSBMHDRC Register Map.................................................................................. 23

3.2. Common Registers..................................................................................................... 29

3.2.1. FAddr............................................................................................... 29

3.2.2. Power............................................................................................... 29

3.2.3. IntrTx .............................................................................................. 30

3.2.4. IntrRx .............................................................................................. 31

3.2.5. IntrTxE ........................................................................................... 32

3.2.6. IntrRxE ........................................................................................... 33

3.2.7. IntrUSB........................................................................................... 33

3.2.8. IntrUSBE ........................................................................................ 34

3.2.9. Frame............................................................................................... 34

3.2.10. Index................................................................................................ 34

3.2.11. TestMode ........................................................................................ 34

3.2.12. DevCtl ............................................................................................. 35

3.2.13. MISC................................................................................................ 36

3.3. Indexed Registers ....................................................................................................... 37

3.3.1. CSR0L ............................................................................................. 37

3.3.2. CSR0H............................................................................................. 39

3.3.3. Count0............................................................................................. 40

3.3.4. Type0 ............................................................................................... 40

3.3.5. ConfigData ..................................................................................... 41

3.3.6. NAKLimit0 .................................................................................... 41

3.3.7. TxMaxP........................................................................................... 42

SBMHDRC PRODUCT

CONFIDENTIAL CONTENTS

MUSBMHDRC

3.3.8.

TxCSRL........................................................................................... 43

3.3.9. TxCSRH.......................................................................................... 45

3.3.10. RxMaxP........................................................................................... 47

3.3.11. RxCSRL........................................................................................... 48

3.3.12. RxCSRH.......................................................................................... 50

3.3.13. RxCount.......................................................................................... 52

3.3.14. TxType............................................................................................. 52

3.3.15. TxInterval ....................................................................................... 53

3.3.16. RxType............................................................................................. 53

3.3.17. RxInterval ....................................................................................... 54

3.3.18. FIFOSize......................................................................................... 54

3.4. FIFOx (Addresses 20h – 5Fh) ................................................................................. 55

3.5. Additional Multipoint Control/Status Registers.................................................... 55

3.5.1. TxFuncAddr/RxFuncAddr.......................................................... 55

3.5.2. TxHubAddr/RxHubAddr............................................................ 56

3.5.3. TxHubPort/RxHubPort............................................................... 56

3.6. Additional Control/Status Registers........................................................................ 56

3.6.1. VControl ......................................................................................... 56

3.6.2. VStatus ............................................................................................ 57

3.6.3. HWVers........................................................................................... 57

3.7. Additional Configuration Registers.......................................................................... 58

3.7.1. EPInfo............................................................................................. 58

3.7.2. RAMInfo......................................................................................... 58

3.7.3. LinkInfo .......................................................................................... 58

3.7.4. VPLen.............................................................................................. 59

3.7.5. HS_EOF1....................................................................................... 59

3.7.6. FS_EOF1........................................................................................ 59

3.7.7. LS_EOF1........................................................................................ 60

3.7.8. SOFT_RST..................................................................................... 60

3.8. Extended Registers..................................................................................................... 60

3.8.1. RqPktCount.................................................................................... 61

3.8.2. Double Packet Buffer Disable...................................................... 61

3.8.2.1. Rx DPktBufDis ................................................. 61

3.8.2.2. Tx DPktBufDis ................................................. 62

3.8.3. C_T_UCH ...................................................................................... 63

3.8.4. C_T_HSRTN ................................................................................. 64

3.8.5. C_T_HSBT..................................................................................... 64

3.9. DMA Registers ........................................................................................................... 65

3.9.1. DMA_INTR................................................................................... 65

3.9.2. DMA_CNTL.................................................................................. 66

3.9.3. DMA_ADDR................................................................................. 67

3.9.4. DMA_COUNT.............................................................................. 67

CONTENTS CONFIDENTIAL

MUSBMHDRC PRODUCT SPECIFICATION

AND PROGRAMMER’S GUIDE

3.10. Dynamic Fifo Registers ........................................................................................... 68

3.10.1. TxFIFOsz ....................................................................................... 68

3.10.2. RxFIFOsz ....................................................................................... 69

3.10.3. TxFIFOadd..................................................................................... 70

3.10.4. RxFIFOadd .................................................................................... 70

4. CLOCKING AND RESET..................................................................................... 70

4.1. Clocking....................................................................................................................... 70

4.2. Reset............................................................................................................................. 71

5. CPU INTERFACE .................................................................................................... 72

6. DATA WIDTH.......................................................................................................... 72

7. RAM INTERFACE................................................................................................... 73

8. USB INTERFACE .................................................................................................... 73

8.1. Optional USB 1.1 PHY Interface ............................................................................ 76

8.1.1. The Standard USB 1.1 PHY Interface........................................ 77

8.1.2. USB 1.1 PHY Interface with I

C-bus Control Option............. 78

8.2. Soft Connect/Disconnect......................................................................................... 79

8.3. Bus Turn-Around Time Considerations ................................................................. 80

8.4. Operation as a Peripheral.......................................................................................... 81

8.4.1. IN Transaction Handling as a Peripheral.................................... 81

8.4.1.1. Single Packet Buffering..................................... 81

8.4.1.2. Double Packet Buffering.................................. 82

8.4.1.3. High Bandwidth Isochronous/Interrupt

Endpoints........................................................... 83

8.4.1.4. Optional Special Handling ............................... 84

8.4.2. OUT Transaction Handling as a Peripheral ............................... 85

8.4.2.1. Single Packet Buffering..................................... 85

8.4.2.2. Double Packet Buffering.................................. 85

8.4.2.3. High Bandwidth Isochronous/Interrupt

Endpoints........................................................... 86

8.4.2.4. Optional Special Handling ............................... 88

8.4.3. Additional Actions......................................................................... 89

STALL issued TO CONTROL TRANSFER.................. 89

ZERO LENGth OUT DATA PACKETS in Control

Transfers............................................................. 89

8.4.4. Peripheral Mode Suspend............................................................. 90

8.4.5. Start-Of-Frame............................................................................... 90

8.5. Operation as a Host................................................................................................... 90

8.5.1. Device Set-up FOR MULTIPOINT CONFIGURATION.... 90

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