usb2.0 utmi协议

utmi

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USB 2.0

Transceiver Macrocell Interface

(UTMI)

Specification

Version 1.05

3/29/2001

Please send comments via electronic mail to:

steve.mcgowan@intel.com

USB2.0 Transceiver Macrocell

Table of Contents

1 Preface ....................................................................................................................................................7

1.1 Scope of this Revision.....................................................................................................................7

1.2 Revision History .............................................................................................................................7

2 Introduction.............................................................................................................................................9

2.1 USB 2.0 Transceiver Macrocell (UTM) .........................................................................................9

2.2 Serial Interface Engine..................................................................................................................10

2.3 Device Specific Logic...................................................................................................................10

3 Functional Block Diagram....................................................................................................................11

4 UTMI Signal Descriptions....................................................................................................................12

4.1 System Interface Signals...............................................................................................................12

4.1.1 CLK ......................................................................................................................................13

4.1.1.1 Options..............................................................................................................................13

4.1.2 XcvrSelect.............................................................................................................................13

4.1.3 TermSelect............................................................................................................................13

4.1.4 LineState ............................................................................................................................... 13

4.1.4.1 Synchronization ................................................................................................................13

4.1.4.2 Signaling Levels................................................................................................................14

4.1.4.3 Minimizing Transitions.....................................................................................................14

4.1.4.4 Bus Packet Timing............................................................................................................15

4.1.5 OpMode ................................................................................................................................15

4.2 USB Interface Signals................................................................................................................... 15

4.3 Vendor Control Signals.................................................................................................................16

4.4 Data Interface Signals...................................................................................................................17

4.4.1 Receive Active......................................................................................................................18

5 Block level Descriptions.......................................................................................................................21

5.1 Clock Multiplier............................................................................................................................21

5.1.1 Clocking................................................................................................................................21

5.1.1.1 HS/FS operation................................................................................................................21

5.1.1.2 FS Only operation.............................................................................................................22

5.1.1.3 LS Only operation.............................................................................................................22

5.2 HS DLL (High Speed Delay Line PLL) .......................................................................................22

5.3 Elasticity Buffer............................................................................................................................22

5.4 Mux............................................................................................................................................... 22

5.5 NRZI Decoder............................................................................................................................... 23

5.6 Bit Unstuff Logic..........................................................................................................................23

5.7 Rx Shift/Hold Register..................................................................................................................23

5.8 Receive State Machine..................................................................................................................23

5.8.1 Receive Error Reporting .......................................................................................................27

5.8.1.1 Bit Suff Error Reporting....................................................................................................27

5.9 Rx Shift/Hold Registers ................................................................................................................28

5.10 NRZI Encoder...............................................................................................................................29

5.11 Bitstuff Logic................................................................................................................................29

5.12 Tx Shift/Hold Register.................................................................................................................. 29

5.13 Transmit State Machine ................................................................................................................ 30

5.13.1 Transmit Error Reporting......................................................................................................31

5.14 USB Full Speed XCVR.................................................................................................................32

5.14.1 Transmit Driver..................................................................................................................... 32

5.14.2 Receive Buffer ......................................................................................................................32

5.15 USB2.0 XCVR..............................................................................................................................32

5.15.1 Transmit Driver..................................................................................................................... 32

5.15.2 Receive Buffer ......................................................................................................................32

5.15.3 Other Components of Transceiver ........................................................................................32

5.15.3.1 Transmission Envelope Detector ..................................................................................32

5.15.3.2 Full-Speed Indicator Control......................................................................................... 32

USB2.0 Transceiver Macrocell

5.16

Operational Modes........................................................................................................................33

5.16.1 USB 2.0 Test Mode Generation............................................................................................ 33

5.17 Speed Selection.............................................................................................................................34

5.18 Bi-directional 8-bit Interface......................................................................................................... 34

5.19 16-Bit Interface.............................................................................................................................35

5.19.1 16-Bit Transmit Timing ........................................................................................................36

5.19.2 16-Bit Receive Timing..........................................................................................................37

5.20 Bi-directional 16-bit Interface....................................................................................................... 38

5.21 Vendor Controls............................................................................................................................39

5.22 Other Functions.............................................................................................................................40

5.22.1 SE0 handling.........................................................................................................................40

5.22.1.1 Suspend Detection......................................................................................................... 41

5.22.1.2 Reset Detection .............................................................................................................42

5.22.2 HS Detection Handshake ......................................................................................................43

5.22.2.1 FS Downstream Facing Port ......................................................................................... 45

5.22.2.2 HS Downstream Facing Port......................................................................................... 46

5.22.2.3 Suspend Timing ............................................................................................................ 48

5.22.3 Assertion of Resume.............................................................................................................50

5.22.4 Detection of Resume.............................................................................................................51

5.22.5 HS Device Attach..................................................................................................................52

6 Appendix...............................................................................................................................................53

6.1 FS Operations................................................................................................................................53

6.1.1 FS Start Of Packet.................................................................................................................53

6.1.2 FS End Of Packet..................................................................................................................53

6.2 HS Operation ................................................................................................................................ 55

6.2.1 HS Start Of Packet................................................................................................................55

6.2.2 HS End Of Packet.................................................................................................................55

6.3 Timing Constraints........................................................................................................................57

6.4 Inter-Packet Delay Overview........................................................................................................58

6.4.1 HS Inter-packet delay for a receive followed by a transmit..................................................58

6.4.2 HS Inter-packet delay for a receive followed by a receive ...................................................61

6.4.3 FS Inter-packet delay for a Receive followed by a Transmit................................................62

6.4.3.1 HS/FS UTM is running in Full Speed mode..................................................................... 62

6.4.3.2 FS Only or LS Only UTMs............................................................................................... 63

6.4.4 FS Inter-packet delay for a Transmit followed by a Receive................................................63

6.4.4.1 HS/FS UTM is running in Full Speed mode..................................................................... 63

6.4.4.2 FS Only or LS Only UTMs............................................................................................... 64

6.4.4.3 Full Speed Transmit.......................................................................................................... 64

6.4.4.4 Full Speed Receive............................................................................................................ 65

6.5 UTM Entity Diagrams ..................................................................................................................66

USB2.0 Transceiver Macrocell

Table of Figures

Figure 1: ASIC Functional Blocks..................................................................................................................9

Figure 2: UTM Functional Block Diagram...................................................................................................11

Figure 3: FS CLK Relationship to Receive Data and Control Signals..........................................................21

Figure 4: FS CLK Relationship to Transmit Data and Control Signals........................................................ 22

Figure 5: Receive Timing for Data with after Unstuffing Bits .....................................................................23

Figure 6: Receive State Diagram .................................................................................................................. 24

Figure 7: Receive Timing for Data Packet (with CRC-16)...........................................................................25

Figure 8: Receive Timing for Setup Packet..................................................................................................26

Figure 9: Receive Timing for a Handshake Packet (no CRC)......................................................................26

Figure 10: RXError Timing diagram............................................................................................................27

Figure 11: Transmit Timing delays due to Bit Stuffing................................................................................29

Figure 12: Transmit State Diagram............................................................................................................... 30

Figure 13: Transmit Timing for a Data packet..............................................................................................31

Figure 14: 8-Bit Bi-directional Data Bus Interface.......................................................................................34

Figure 15: Transmit Timing for 16-bit Data, Even Byte Count....................................................................36

Figure 16: Transmit Timing for 16-bit Data, Odd Byte Count .....................................................................36

Figure 17: Receive Timing for 16-bit Data, Even Byte Count .....................................................................37

Figure 18: Receive Timing for 16-bit Data, Odd Byte Count.......................................................................37

Figure 19: 16-bit Bi-directional Data Bus Interface......................................................................................38

Figure 20: Vendor Control Register Block Diagram ....................................................................................39

Figure 21: Suspend Timing Behavior (HS Mode)........................................................................................41

Figure 22: Reset Timing Behavior (HS Mode)............................................................................................. 42

Figure 23: HS Detection Handshake Timing Behavior (FS Mode)..............................................................45

Figure 24: Chirp K-J-K-J-K-J Sequence Detection State Diagram ..............................................................46

Figure 25: HS Detection Handshake Timing Behavior (HS Mode)..............................................................47

Figure 26: HS Detection Handshake Timing Behavior from Suspend .........................................................48

Figure 27: Resume Timing Behavior (HS Mode).........................................................................................50

Figure 28: Device Attach Behavior ..............................................................................................................52

Figure 29: Data Encoding Sequence: FS SYNC...........................................................................................53

Figure 30: Data Encoding Sequence: FS EOP..............................................................................................54

Figure 31: Data Encoding Sequence: HS SYNC ..........................................................................................55

Figure 32: Data Encoding Sequence: HS EOP .............................................................................................56

Figure 33: Timing Constraints...................................................................................................................... 57

Figure 34: HS Receive to transmit inter-packet delay .................................................................................. 58

Figure 35: HS Transmit to Receive inter-packet delay................................................................................. 60

Figure 36: HS Back to back receives with minimum inter-packet delay......................................................61

Figure 37: FS Receive to transmit inter-packet delay................................................................................... 62

Figure 38: FS transmit to receive or receive to receive inter-packet delay...................................................63

Figure 39: Start of FS handshake transmit....................................................................................................64

Figure 40: 8-Bit Interface Entity Diagram....................................................................................................66

Figure 41: 16-Bit Interface Entity Diagram..................................................................................................66

Figure 42: 8-Bit Bi-directional Interface Entity Diagram.............................................................................67

Figure 43: 16-Bit Bi-directional Interface Entity Diagram...........................................................................67

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