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首页24C02 PDF和中文资料
24C02 PDF和中文资料
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24C02 串行E2PROM是基于I2C-BUS 的存储器件,遵循二线制协议,由于其具有接口方便,体积小,数据掉电不丢失等特点,在仪器仪表及工业自动化控制中得到大量的应用
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1996 Microchip Technology Inc.
Preliminary
DS21170A-page 1
FEATURES
• ISO Standard 7816 pad locations
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• Two-wire serial interface bus, I
2
C
compatible
• 100 kHz and 400 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24C01SC and
24C02SC are 1K-bit and 2K-bit Electrically Erasable
PROMs with bondpad positions optimized for smart
card applications. The devices are organized as a sin-
gle block of 128 x 8-bit or 256 x 8-bit memory with a
two-wire serial interface. The 24C01SC and 24C02SC
also have page-write capability for up to 8 bytes of data.
- Commercial (C): 0
°
C to +70
°
C
DIE LAYOUT
BLOCK DIAGRAM
SDA
DC
V
CC
SCL
V
SS
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
SDA SCL
VCC
VSS
1K/2K 5.0V I
2
C Serial EEPROMs for Smart Cards
24C01SC/02SC
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker404
24C01SC/02SC
DS21170A-page 2
Preliminary
1996 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Maximum Ratings*
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
......-0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
ESD protection on all pads
.....................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PAD FUNCTION TABLE
Name Function
V
SS
SDA
SCL
V
CC
DC
Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
Don’t connect
TABLE 1-2: DC CHARACTERISTICS
FIGURE 1-1: BUS TIMING START/STOP
V
CC
= +4.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pads:
High level input voltage V
IH
.7 V
CC
——
Low level input voltage V
IL
— .3 V
CC
V
Hysteresis of Schmidt trigger inputs V
HYS
.05 V
CC
— V (Note)
Low level output voltage V
OL
— .40 V I
OL
= 3.0 mA, V
CC
= 4.5V
Input leakage current (SCL) I
LI
-10 10
µ
AV
IN
= .1V to 5.5V
Output leakage current (SDA) I
LO
-10 10
µ
AV
OUT
= .1V to 5.5V
Pin capacitance (all inputs/outputs) C
IN
,
C
OUT
—10pFV
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
Operating current I
CC
Write — 3 mA V
CC
= 5.5V
I
CC
Read — 1 mA Vcc = 5.5V, SCL = 400 KHz
Standby current I
CCS
— 100
µ
AV
CC
= 5.5V, SDA = SCL = V
CC
Note: This parameter is periodically sampled and not 100% tested.
SCL
SDA
T
SU:STA
THD:STA
START STOP
VHYS
TSU:STO
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 3
24C01SC/02SC
TABLE 1-3: AC CHARACTERISTICS
FIGURE 1-2: BUS TIMING DATA
Parameter Symbol Min. Max. Units Remarks
Clock frequency F
CLK
— 400 kHz
Clock high time T
HIGH
600 — ns
Clock low time T
LOW
1300 — ns
SDA and SCL rise time T
R
— 300 ns (Note 1)
SDA and SCL fall time T
F
— 300 ns (Note 1)
START condition hold time T
HD
:
STA
600 — ns After this period the first clock
pulse is generated
START condition setup time T
SU
:
STA
600 — ns Only relevant for repeated
START condition
Data input hold time T
HD
:
DAT
0 — ns (Note 2)
Data input setup time T
SU
:
DAT
100 — ns
STOP condition setup time T
SU
:
STO
600 — ns
Output valid from clock T
AA
— 900 ns (Note 2)
Bus free time T
BUF
1300 — ns Time the bus must be free
before a new transmission can
start
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
20 +0.1
CB
250 ns (Note 1), CB
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
— 50 ns (Note 3)
Write cycle time T
WR
— 10 ms Byte or Page mode
Endurance —
10
6
— cycles 25
°
C, Vcc = 5V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
HD:STA
TSU:STA
TF
THIGH
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
THD:STA
TAA
TSP
TLOW
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