Constraining and Analyzing Source-Synchronous Interfaces

© March 2010 Altera Corporation AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN-433-2.2© March 2010

AN 433: Constraining and Analyzing

Source-Synchronous Interfaces

This application note describes techniques for constraining and analyzing

source-synchronous interfaces. In source-synchronous interfaces, the source of the

clock is the same device as the source of the data, rather than another source, such as a

common clock network.

Figure 1 shows a block diagram of a basic source-synchronous interface.

analyzer before you read this application note.

f For more information, refer to the SDC and TimeQuest API Reference Manual and the

This application note is divided into two main sections:

■ “Source-Synchronous Outputs” on page 6

■ “Source-Synchronous Inputs” on page 42

These sections include descriptions of the output and input interfaces and details

about the three types of SDC constraints or exceptions that apply to each direction.

You can use a script included with the Quartus

II software installation to guide you

Some source-synchronous interfaces use a clock that is edge-aligned with the data, as

phase-locked loop (PLL) shifts the input clock, which is then used to latch the data. If

a PLL shifts the input clock, you can adjust the clock and data timing relationship by

adjusting the PLL phase offset.

In source-synchronous SDR interfaces, one edge of the clock, typically the rising edge,

transfers the data, as shown in Figure 4. The time required to transmit one bit, known

as the unit interval (UI), is equal to the period of the clock.

© March 2010 Altera Corporation AN 433: Constraining and Analyzing Source-Synchronous Interfaces

In source-synchronous DDR interfaces, data is transferred on both edges of the clock,

constraints to apply to the same port.

exceptions:

■ Clock constraints—Define the clocks used in the interface. Clock constraints

define the period and include any other clock characteristics such as offset and

■ Input or output delay constraints—Describe the required times for data to be

valid at the interface. Input and output delay constraints are derived from timing

parameters, such as skew, t

that specify the interface operation.

rising clock edge is latched by the next rising clock edge. Source-synchronous

interfaces, however, often exhibit different behavior. Data may be latched by the same

edge that launches it, and source-synchronous DDR interfaces launch and latch data

on rising and falling clock edges.

© March 2010 Altera Corporation AN 433: Constraining and Analyzing Source-Synchronous Interfaces

Figure 6 shows the setup relationships analyzed by default in an edge-aligned DDR

interface. Solid red arrows indicate same-edge transfers (rise-to-rise and fall-to-fall),

and dashed red arrows indicate opposite-edge transfers (rise-to-fall and fall-to-rise).

Figure 7 shows the hold relationships analyzed by default in an edge-aligned DDR

interface. Solid blue arrows indicate hold relationships for same-edge transfers

(rise-to-rise and fall-to-fall), and dashed blue arrows indicate hold relationships for

opposite-edge transfers (rise-to-fall and fall-to-rise).

Figure 8 shows the setup relationships analyzed by default in a center-aligned DDR

interface. Solid red arrows indicate same-edge transfers (rise-to-rise and fall-to-fall),

and dashed red arrows indicate opposite-edge transfers (rise-to-fall and fall-to-rise).