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Version: 1.03
Release date: 2010-04-20
© 2010 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
MT6253 GSM/GPRS SOC Processor
Data Sheet
MEDIATEK Confidential Release for
Phoenix_WCX
MEDIATEK Confidential Release for
Phoenix_WCX
![](https://csdnimg.cn/release/download_crawler_static/2831218/bg2.jpg)
MT6253
GSM/GPRS SOC Processor Data Sheet
v1.03 Confidential A
MediaTek Confidential © 2010 MediaTek Inc. Page 2 of 660
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Revision History
Revision Date Comments
1.00 Nov 7, 2009 Formal release
1.01 Jan 12, 2010 1. Remove UART2 HW flow control
2. Add MT6253AN for 261 pin LF
3. Remove nand booting section
4. UVLO spec revision
5. boost on threshold voltage revision
6. MPLL output frequency revision
7. class-D output wattage spec revision
8. boost output voltage range revision
9. charger voltage OV and OV recovery spec revision
10. charger detection on / off threshold revision
11. charger pre-charger to CC mode threshold revision
12. charger CC mode current spec revision
13. KP_LED spec revision (Vout < 1V @ Isink=150mA)
14. remove RLED circuit to fit EM rule but still pass Vout < 1V @ Isink=150mA
15. buck output / line regulation / load regulation spec revision
16. LDO output / line / load regulation spec revision as the specific range
17. modify VRF LDO max current but maintain the current limit spec
18. modify VA LDO max current but maintain the current limit spec
19. modify VUSB LDO max current but maintain the current limit spec
20. LDO turn-on rise time revision
21. RTC oscillator min. sustained voltage
22. add one extra register bit for CV tunning, using reserved bit
23. camera spec update
24. LCD spec update
1.02 Mar. 10, 2010
1. Pin map problem: C19 should be VIBRATOR, K2 should be VBT
2. LDO max current specification revised
3. Section “General Purpose Inputs/Outputs”, correct some GPIO mode selection description
from “GPI” to “GPIO”.
1.03 Apr. 15, 2010
1. Add PMU system block diagram.
2. Add part number of security version.
3. J3 should be SPK1_N, K4 should be SPK1_P: the purpose is to align the output phase with
audio output
4. Add MT6253A in system overview section.
5. Remove MT6253 Software Programming Specification in section 3.2.1.3.2 Factory
programming.
6. Remove nand booting.
MEDIATEK Confidential Release for
Phoenix_WCX
MEDIATEK Confidential Release for
Phoenix_WCX
![](https://csdnimg.cn/release/download_crawler_static/2831218/bg3.jpg)
MT6253
GSM/GPRS SOC Processor Data Sheet
v1.03 Confidential A
MediaTek Confidential © 2010 MediaTek Inc. Page 3 of 660
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MEDIATEK Confidential Release for
Phoenix_WCX
MEDIATEK Confidential Release for
Phoenix_WCX
![](https://csdnimg.cn/release/download_crawler_static/2831218/bg4.jpg)
MT6253
GSM/GPRS SOC Processor Data Sheet
v1.03 Confidential A
MediaTek Confidential © 2010 MediaTek Inc. Page 4 of 660
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
TABLE OF CONTENTS
Revision History ...................................................................................................................................... 2
Preface...................................................................................................................................................... 6
1 System Overview ............................................................................................................................... 8
1.1 Platform Features ...................................................................................................................................................... 11
1.2 MODEM Features .................................................................................................................................................... 12
1.3 Multi-Media Features ............................................................................................................................................... 13
1.4 General Description ................................................................................................................................................. 15
2 Product Description ........................................................................................................................ 17
2.1 Pin Outs .................................................................................................................................................................... 17
2.2 Top Marking Definition ........................................................................................................................................... 27
2.3 DC Characteristics ................................................................................................................................................... 28
2.4 Pin Description ......................................................................................................................................................... 31
2.5 Paddle Description ................................................................................................................................................... 40
3 Micro-Controller Unit Subsystem ................................................................................................. 41
3.1 Processor Core ......................................................................................................................................................... 42
3.2 Memory Management .............................................................................................................................................. 42
3.3 Bus System............................................................................................................................................................... 46
3.4 Direct Memory Access ............................................................................................................................................. 50
3.5 Code Cache controller .............................................................................................................................................. 71
3.6 Interrupt Controller .................................................................................................................................................. 80
3.7 MPU ......................................................................................................................................................................... 98
3.8 Internal Memory Interface ..................................................................................................................................... 107
3.9 External Memory Interface .................................................................................................................................... 108
4 Microcontroller Peripherals ........................................................................................................ 124
4.1 Pulse-Width Modulation Outputs ........................................................................................................................... 124
4.2 Alerter .................................................................................................................................................................... 127
4.3 SIM Interface ......................................................................................................................................................... 130
4.4 Keypad Scanner ..................................................................................................................................................... 142
4.5 General Purpose Inputs/Outputs ............................................................................................................................ 146
4.6 General Purpose Timer ........................................................................................................................................... 174
4.7 UART ..................................................................................................................................................................... 178
4.8 IrDA Framer ........................................................................................................................................................... 200
4.9 Real Time Clock .................................................................................................................................................... 210
4.10 Auxiliary ADC Unit ............................................................................................................................................... 219
4.11 I2C / SCCB Controller ........................................................................................................................................... 226
5 Microcontroller Coprocessors ..................................................................................................... 238
5.1 Divider ................................................................................................................................................................... 238
5.2 CSD Accelerator .................................................................................................................................................... 241
5.3 FCS Codec ............................................................................................................................................................. 254
5.4 GPRS Cipher Unit .................................................................................................................................................. 257
6 Multi-Media Subsystem ............................................................................................................... 260
6.1 LCD Interface ........................................................................................................................................................ 260
MEDIATEK Confidential Release for
Phoenix_WCX
MEDIATEK Confidential Release for
Phoenix_WCX
![](https://csdnimg.cn/release/download_crawler_static/2831218/bg5.jpg)
MT6253
GSM/GPRS SOC Processor Data Sheet
v1.03 Confidential A
MediaTek Confidential © 2010 MediaTek Inc. Page 5 of 660
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
6.2 Image Resizer ......................................................................................................................................................... 303
6.3 NAND FLASH interface ....................................................................................................................................... 324
6.4 USB 2.0 High-Speed Dual-Role Controller ........................................................................................................... 348
6.5 Memory Stick and SD Memory Card Controller ................................................................................................... 392
6.6 Camera Interface .................................................................................................................................................... 420
7 Audio Front-End ........................................................................................................................... 433
7.1 General Description ............................................................................................................................................... 433
7.2 Register Definitions ............................................................................................................................................... 436
7.3 Programming Guide ............................................................................................................................................... 452
8 Radio Interface Control ............................................................................................................... 454
8.1 Baseband Serial Interface ....................................................................................................................................... 454
8.2 Baseband Parallel Interface .................................................................................................................................... 462
8.3 Automatic Power Control (APC) Unit ................................................................................................................... 467
9 Baseband Front End ..................................................................................................................... 474
9.1 Baseband Serial Ports ............................................................................................................................................. 475
9.2 Downlink Path (RX Path) ...................................................................................................................................... 478
9.3 Uplink Path (TX Path) ........................................................................................................................................... 487
10 Timing Generator ......................................................................................................................... 492
10.1 TDMA timer ........................................................................................................................................................... 492
11 Power, Clocks and Reset .............................................................................................................. 507
11.1 Clocks .................................................................................................................................................................... 507
11.2 Reset Generation Unit (RGU) ................................................................................................................................ 520
11.3 Software Power Down Control .............................................................................................................................. 524
12 Analog Front-end & Analog Blocks ............................................................................................ 531
12.1 General Description ............................................................................................................................................... 531
12.2 ABB Register Definitions ...................................................................................................................................... 543
12.3 PMU Registers Definition ...................................................................................................................................... 578
12.4 Programming Guide ............................................................................................................................................... 636
13 RFSYS ............................................................................................................................................ 650
13.1 General Description ............................................................................................................................................... 650
13.2 Functional Block Diagram ..................................................................................................................................... 651
13.3 Pins and I/O Ports Description ............................................................................................................................... 651
13.4 Electrical Characteristic ......................................................................................................................................... 653
MEDIATEK Confidential Release for
Phoenix_WCX
MEDIATEK Confidential Release for
Phoenix_WCX
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