"ARM64 过程调用标准1.3最新发布及缺陷报告概述"

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Issue Date Change

2019Q4 30th January 2020 Github release with an open source license.

Major changes:

1. New Licence, with relative explanation in About the license.

2. New sections on Contributions, Trademark notice, and Copyright.

3. Specify that the frame chain should use the signed return address (The

Frame Pointer)

4. Add description of half-precision Brain floating-point format

(Half-precision Floating Point, Half-precision Format Compatibility,

Arithmetic Types, Types Varying by Data Model, APPENDIX Support

for Advanced SIMD Extensions)

5. Update C++ mangling to reflect existing practice (APPENDIX C++

Mangling).

Minor changes:

1. The section Bit-fields subdivision has been renamed to make the

associated implicit link target unique and avoid clashing with the one of

Bit-fields.

2. Several formatting changes have been applied to the sources to fix the

rendered page produced by github.

2020Q2 1st July 2020 Add requirements for stack space with MTE tags. Extend the AAPCS64 to

support SVE types and registers. Conform aapcs64 volatile bit-fields rules to

C/C++.

2020Q3 1st October 2020 Specify ABI handling for 8.7-A's new FPCR bits.

2021Q1 12

April 2021

• Clarify rule C.4 of the Parameter Passing Rules when there is an

overaligned HFA.

• Minor formatting changes.

2.1.3 References

This document refers to, or is referred to by, the following documents:

Ref URL or other reference Title

AAPCS64 Source for this document Procedure Call Standard for the Arm 64-bit

Architecture

CPPABI64 IHI 0059 C++ ABI for the Arm 64-bit Architecture

GC++ABI https://itanium-cxx-abi.github.io/cxx-abi/abi.html Generic C++ ABI

2.2 Terms and Abbreviations

2.2.1 This document uses the following abbreviations

A32

The instruction set named Arm in the Armv7 architecture; A32 uses 32-bit fixed-length instructions.

A64

The instruction set available when in AArch64 state.

AAPCS64

Procedure Call Standard for the Arm 64-bit Architecture (AArch64)

AArch32

The 32-bit general-purpose register width state of the Armv8 architecture, broadly compatible with the Armv7-A

architecture.

AArch64

The 64-bit general-purpose register width state of the Armv8 architecture.

ABI

Application Binary Interface:

1. The specifications to which an executable must conform in order to execute in a specific execution

environment. For example, the Linux ABI for the Arm Architecture.

2. A particular aspect of the specifications to which independently produced relocatable files must conform in

order to be statically linkable and executable. For example, the CPPABI64, AAELF64, ...

Arm-based

... based on the Arm architecture ...

Floating point

Depending on context floating point means or qualifies: (a) floating-point arithmetic conforming to IEEE 754 2008;

(b) the Armv8 floating point instruction set; (c) the register set shared by (b) and the Armv8 SIMD instruction set.

Q-o-I

Quality of Implementation – a quality, behavior, functionality, or mechanism not required by this standard, but

which might be provided by systems conforming to it. Q-o-I is often used to describe the tool-chain-specific

means by which a standard requirement is met.

MTE

The Arm architecture's Memory Tagging Extension.

SIMD

Single Instruction Multiple Data – A term denoting or qualifying: (a) processing several data items in parallel

under the control of one instruction; (b) the Arm v8 SIMD instruction set: (c) the register set shared by (b) and the

Armv8 floating point instruction set.

SIMD and floating point

The Arm architecture’s SIMD and Floating Point architecture comprising the floating point instruction set, the

SIMD instruction set and the register set shared by them.

SVE

The Arm architecture's Scalable Vector Extension.

T32

The instruction set named Thumb in the Armv7 architecture; T32 uses 16-bit and 32-bit instructions.

The number of 64-bit “vector granules” in an SVE vector; in other words, the number of bits in an SVE vector

ILP32

SysV-like data model where int, long int and pointer are 32-bit

LP64

SysV-like data model where int is 32-bit, but long int and pointer are 64-bit.

LLP64

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