Verilog HDL逻辑综合入门指南

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《逻辑合成入门：使用Verilog HDL》是一本由Robert B. Reese和Mitchell A. Thornton合著的专业参考书籍，版权归Morgan & Claypool所有。该书针对逻辑合成领域的新手和专业人士，详细介绍了如何利用Verilog Hardware Description Language (HDL)进行电路设计和逻辑实现。Verilog是电子设计自动化（EDA）中常用的高级硬件描述语言，它提供了强大的抽象和模块化能力，使得设计者能够描述数字电路的行为和结构。本书的主要内容涵盖了逻辑合成的基本概念、Verilog语法规则、设计流程、以及如何使用Verilog进行门级、行为级和系统级的设计。作者在书中强调了Verilog的结构化编程方法，包括组合逻辑、时序逻辑、模块化设计和接口描述。读者可以从中学习到如何编写有效的Verilog代码，包括数据类型、赋值语句、条件语句、循环、并行和同步结构等。章节可能包括： 1. **Verilog概述**：介绍Verilog语言的历史、特点和与传统电路设计语言的区别，以及其在现代电子设计中的重要性。 2. **Verilog基本语法**：讲解Verilog的关键组成部分，如声明、定义、程序块和信号声明，让读者熟悉语言的构造。 3. **逻辑设计基础**：涉及基本逻辑门、触发器、组合逻辑和时序逻辑的实现，以及布尔代数和逻辑优化的基础知识。 4. **模块设计**：教授如何创建独立的、可重用的模块，包括模块参数、端口、包和接口，以及模块间的连接。 5. **设计流程与工具**：讨论逻辑综合的过程，包括逻辑描述、仿真、验证和优化，以及使用Verilog工具（如Quartus II, ISE, or Vivado）的技巧。 6. **高级设计技术**：探讨复杂逻辑结构的实现，如状态机、时序分析、以及高级功能单元的设计如寄存器、计数器和移位寄存器。 7. **案例研究与实践项目**：通过实际案例演示如何将理论知识应用到实际设计中，帮助读者加深理解并提升设计能力。《逻辑合成入门：使用Verilog HDL》作为SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS系列的一部分，旨在提供一个全面而深入的学习平台，适合电子工程专业学生、工程师和研究人员作为教材，或者作为自学的参考资料。无论你是希望进入硬件设计行业，还是想提高现有设计技能，这本书都能提供关键的指导和支持。

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MOBK046-01 MOBK046-Thornton.cls October 14, 2006 13:14

6 INTRODUCTION TO LOGIC SYNTHESIS USING VERILOG HDL

FIGURE 1.5: One-bit 2-to-1 multiplexer implementations using assign statements

written, so the interface of the three modules remains the same. These examples have the input

signals ﬁrst, followed by the output signal, but the order is arbitrary. The

input and output

statements that follow the module declaration deﬁne the direction of each interface signal. A

port is declared bidirectional by using the

inout keyword. These examples list all of the input

ports using a single

input statement; individual input statements could have also been used.

Our examples use lowercase for user-deﬁned names such as module and port names; uppercase

is commonly used as well. It is suggested that mixed case not be used for user-deﬁned names,

as the tools that operate on the design data after they have been transformed from Verilog to

some intermediate format may have difﬁculty with mixed-case names.

assign statement makes a continuous assignment of the right-side expression to the

net or port that appears on the left side, using the “=” operator. The best way to think of a

continuous assignment is that the right-side expression deﬁnes a block of combinational logic,

whose output is continuously connected, and thus continuously drives, the net or the port on the

left side. Fig. 1.5(a) uses a single

assign statement to specify a 2-to-1 multiplexer using Boolean

operators. Fig. 1.5(b) divides the Boolean operators across multiple

assign statements, using

internal nets (gate ports joined by a wire)

na and nb in the last assign statement to implement

the ﬁnal or gate. The

wire statement is used to declare nets na and nb; this is not strictly

necessary as only multibit nets (busses) have to be explicitly declared. Fig. 1.5(c) uses the

conditional operator “?” in a single assignment to specify the multiplexer logic. The ﬁrst operand

in the conditional operator is the select operand (i.e.,

s); if this operand evaluates as nonzero then

the second operand (i.e.,

a) is evaluated and returned, else the third operand is evaluated and

returned. A module is terminated using the

endmodule keyword. All of these implementations

result in the same logic; none of them have any inherent advantages over the others.

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MOBK046-01 MOBK046-Thornton.cls October 14, 2006 13:14

DIGITAL LOGIC REVIEW WITH VERILOG QUICKSTART 9

of an always block can be one or more statements; begin and end keywords are used to

group multiple statements. The statement “

reg y;

” is included in each of the three modules

of Fig. 1.8 as any net that is assigned within an

always block must be declared as a reg type;

this does not imply that this net is driven by a register or sequential logic.

Fig. 1.8(a) implements the multiplexer using an

if-else statement, with the if-body

evaluated for a nonzero (true) conditional expression and the

else clause evaluated otherwise.

Keywords

begin

and end can be used to place multiple statements in an if-body or else clause.

Fig. 1.8(b) implements the multiplexer using Boolean operators, while Fig. 1.8(c) distributes

the Boolean operators using intermediate nets and multiple assignments. The “=” operator

when used in an

always block is called a blocking assignment, this terminology is discussed in

more detail in Section 1.6, which covers event-driven simulation principles. The

always block

of Fig. 1.8(c) uses an implicit event list designated by “

∗

,” which means that all nets on the

right side of the assignments are included in the event list.

The semantics of the net assignments in an

always blocks differs signiﬁcantly from

assign

statements in that statements in an

always

block use the same sequential execution

model as the statements in an HLL.

•

The logic synthesized for an

always block duplicates the assignments’ behavior as-

suming that the assignments are evaluated sequentially. This means that the order in

which assignments are written in an

always blocks affects the logic that is synthesized.

•

Because of the sequential nature of an

always block, the same net can be assigned

multiple times in an

always block; the last assignment takes precedence.

Fig. 1.9 shows a case in which multiple blocking assignments are made to a net in the same

always block, with assignment ordering affecting the synthesized logic. In Fig. 1.9(a), the

clr input takes precedence over the ld input if both are “1,” while in Fig. 1.9(b) the opposite

holds true. Observe that in the two

always blocks, if both ld and clr are “0,” then the initial

assignment of

q=q old sets the value of q. This is a common coding style used in combinational

logic

always blocks in that a default assignment is made to an output at the block’s beginning,

which is then overridden by later assignments in the block based upon the assertion of other

inputs.

The use of a default assignment to the output net of a combinational

always block

guarantees that the output net is the target of an assignment for any input combination. If there

is some logic path through the

always block that does not assign a value to the output net, then

a latch is inferred on that output as shown in Fig. 1.10. A latch is a sequential logic element,

and should not be synthesized in an

always block that is meant to implement combinational

logic. Inferred latches are a common coding mistake for users who are new to Verilog and logic

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