"DP转接驱动器TI-SN65DP141.pdf详细介绍及示例"

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The TI-SN65DP141 is a DisplayPort (DP) to LVDS converter driver that is designed to facilitate the connection between GPUs and DisplayPort monitors. It features various inputs and outputs for different signals, including HPD, ML, AUXp, and AUXn. The converter driver supports up to four DP channels, allowing for high-quality video and audio transmission. The product comes in a small form factor and is easy to integrate into existing systems. The DP converter driver is equipped with multiple DisplayPort connectors for easy connectivity to GPUs and monitors. The HPD signal is used to detect the presence of a monitor, while the ML signals carry the video and audio data. The AUXp and AUXn signals are used for auxiliary functions such as control and configuration. The converter driver can support up to four output channels, allowing for flexibility in terms of display configuration. The product is compatible with a wide range of GPUs and monitors, making it a versatile solution for various applications. The converter driver is ideal for use in gaming systems, high-definition displays, and other multimedia applications. It can support high-resolution video and audio formats, ensuring a seamless viewing experience for users. In conclusion, the TI-SN65DP141 DisplayPort converter driver is a reliable and efficient solution for connecting GPUs to DisplayPort monitors. With its multiple inputs and outputs, compact design, and high compatibility, this product is suitable for a wide range of applications. Users can expect high-quality video and audio transmission with this converter driver, making it a valuable addition to any system.

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SN65DP141

www.ti.com.cn

ZHCSEQ7 –FEBRUARY 2016

(1) Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 5 and Figure 7.

(2) t

SK(O

) is the magnitude of the time difference between the channels.

(3) t

SK(PP)

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same

(4) All noise sources added.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)

Rise time

(1)

Input signal with 30 ps rise time, 20% to 80%,

ee Figure 7

31 ps

Fall time

(1)

Input signal with 30 ps fall time, 20% to 80%,

See Figure 7

32 ps

SDD22 Differential output return loss

6 GHz (12 Gbps) -14 dB

4.05 GHz (HBR3, 8.1 Gbps) –9.33 dB

4.05 GHz (HBR3, 8.1 Gbps) –6.35 dB

1.35 GHz (HBR, 2.7Gbps) –3.5 dB

PLH

Low-to-high propagation delay

See Figure 6

65 ps

PHL

High-to-low propagation delay 65 ps

SK(O)

Inter-Pair (lane to lane) output skew

(2)

All outputs terminated with 100 Ω,

See Figure 8

8 ps

SK(PP)

Part-to-part skew

(3)

All outputs terminated with 100 Ω 50 ps

Single ended output resistance

Single ended on-chip termination to V

Outputs are AC coupled

50 Ω

Output termination mismatch at 1 MHz 5%

Channel-to-channel isolation Frequency at 6 GHz 35 45 dB

Output referred noise

(4)

10 MHz to 6 GHz, No other noise source present,

= LOW

400 µVRMS

10M Hz to 6 GHz, No other noise source present,

= HIGH

500 µVRMS

EQUALIZATION

G At 6 GHz input signal Equalization Gain, EQ = MAX 15 dB

(pre)

Output pre-cursor pre-emphasis

Input signal with 3.75 pre-cursor and measure it on

the output signal,

See Figure 9

3.75 dB

(pst)

Output post-cursor pre-emphasis

Input signal with 12 dB post-cursor and measure it

on the output signal,

See Figure 9

12 dB

6.7 Switching Characteristics, I

C Interface

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

SCL

SCL clock frequency 400 KHz

BUF

Bus free time between START and STOP conditions 1.3 µs

HDSTA

"Hold time after repeated START condition.

After this period, the first clock pulse is generated

0.6 µs

LOW

Low period of the SCL clock 1.3 µs

HIGH

High period of the SCL clock 0.6 µs

SUSTA

Setup time for a repeated START condition 0.6 µs

HDDAT

Data HOLD time 0 µs

SUDAT

Data setup time 100 µs

Rise time of both SDA and SCL signals 300 µs

Fall time of both SDA and SCL signals 300 µs

SUSTO

Setup time for STOP condition 0.6 µs

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