绕过D盾IIS防火墙:SQL注入攻防策略与技巧

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本文档主要探讨了如何绕过D盾IIS防火墙在Windows 2003服务器上的SQL注入防御策略。D盾IIS防火墙针对GET、POST、COOKIE等请求类型进行限制,并采用了白名单机制,仅允许预设的特定URL访问。作者通过搭建IIS与PHP、MySQL的环境,展示了三种主要的SQL注入绕过方法: 1. 白名单漏洞利用:在PHP环境中,利用`PATH_INFO`特性,通过在请求路径后附加未被白名单包含的地址,如`/3.php/admin.php?id=1unionselect1,2,schema_namefrominformation_schema.SCHEMATA`,成功绕过了防火墙。 2. 空白字符利用:在MySQL中,空格字符 `%a0` 被发现能够与`SELECT`语句结合,使得防火墙无法识别,从而实现注入。示例为`id=1union%a0select1,2,3fromadmin`。 3. 特殊字符\N:通过在SQL语句开头插入`\N`,作者发现这种特殊转义序列可以避开`UNION SELECT`和`SELECT FROM`检测。例如,`id=\Nunion(select1,schema_name,\Nfrom information_schema.schemata)`。 在IIS与ASP/ASPX和MSSQL的组合中,尽管D盾IIS防火墙具有一定的防护能力,但这些绕过技巧表明攻击者可以通过深入理解系统细节找到漏洞。随着D盾新版的即将发布,预计会有更多的防御措施,但同时,这也提醒开发者和安全专家持续关注并改进Web应用程序的安全性,以应对不断演变的威胁。测试和防御策略的更新对于保障网络环境的安全至关重要。

/// programmable block decoder to support protocols such as 64b66b, 64b67b, 128b130b, 128b132b module mppcs_block_dec #( parameter DW = 32, /// max. data width parameter DATA_WIDTH = 32, parameter HW = 4, /// max. header width 4 parameter ND = 16 /// max. number of data per block parameter DATA_PER_BLOCK = 64, ) ( /// ingress data interface input logic [DW-1:0] data_in, /// ingress data before header extraction input logic in_valid, /// ingress flow control output logic in_ready, /// ingress flow control /// egress data interface output logic block_start, /// block synchronization output logic [HW-1:0] header_out, /// block header output logic [DW-1:0] data_out, /// egress data after header extraction output logic out_valid, /// egress flow control input logic out_ready, /// egress flow control /// control options input [$clog2(DW)-1:0] msb_data, /// number of data bits - 1 input [$clog2(HW)-1:0] msb_header, /// number of header bits - 1 input [$clog2(ND)-1:0] msb_num_data, /// number of data per block - 1 output logic sync_track, /// block sync tracking signal input logic sync_mode, /// 0: use external sync directly, 1 : use internal sync after assertion of external sync input logic [3:0] sync_offset, /// offset between sync and block start signal input logic sync_start, /// external sync input logic enable, /// 0: clock-gated, 1: mission mode input logic bypass, /// 1: data pass-through without header insertion /// clock & reset input clk, input rst ); /// mask unused bits in header and data wire [DW+1 :0] data_msk = {({{(DW-1){1'b0}},1'b1}<<msb_data),1'b0} - 1'b1; wire [DW-1:0] data_eff = data_msk[DW-1:0] & data_in; wire [HW+1 :0] header_msk = {({{(HW-1){1'b0}},1'b1}<<msb_header),1'b0} - 1'b1; /// block synchronization wire block_sync_en = enable & ~bypass; logic [$clog2(ND)-1:0] cnt_block_data,cnt_block_data_nxt; logic sync_start_lat; always @(posedge clk or posedge rst) begin if (rst) sync_start_lat <= 0; else sync_start_lat <= sync_start; end

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