Si4706
Rev. 0.5 7
Table 5. 2-Wire Control Interface Characteristics
1,2,3
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency f
SCL
0 — 400 kHz
SCLK Low Time t
LOW
1.3 — — µs
SCLK High Time t
HIGH
0.6 — — µs
SCLK Input to SDIO
↓ Setup
(START)
t
SU:STA
0.6 — — µs
SCLK Input to SDIO
↓ Hold
(START)
t
HD:STA
0.6 — — µs
SDIO Input to SCLK
↑ Setup t
SU:DAT
100 — — ns
SDIO Input to SCLK
↓ Hold
4, 5
t
HD:DAT
0 — 900 ns
SCLK Input to SDIO
↑ Setup
(STOP)
t
SU:STO
0.6 — — µs
STOP to START Time t
BUF
1.3 — — µs
SDIO Output Fall Time t
f:OUT
— 250 ns
SDIO Input, SCLK Rise/Fall Time t
f:IN
t
r:IN
— 300 ns
SCLK, SDIO Capacitive Loading C
b
——50pF
Input Filter Pulse Suppression t
SP
— — 50 ns
Notes:
1. When V
IO
= 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST
.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4706 delays SDIO by a minimum of 300 ns from the V
IH
threshold of SCLK to comply with the minimum t
HD:DAT
specification.
5. The maximum t
HD:DAT
has only to be met when f
SCL
= 400 kHz. At frequencies below 400 KHz, t
HD:DAT
may be
violated as long as all other timing parameters are met.
20 0.1
C
b
1pF
-----------
+
20 0.1
C
b
1pF
-----------
+
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