英特尔64位至强处理器MP规格升级：1MB一级缓存和高达3GHz速度

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英特尔至强处理器MP规格升级英特尔至强处理器MP是一款基于Intel NetBurst微体系结构的处理器，具有高性能和低功耗的特点。它有两个处理器家族，第一个处理器家族的速度从1.40GHz到1.60GHz，并且有256KB二级高速缓存和512KB或1MB三级高速缓存，这一至强处理器MP家族使用0.18微米制程制造。第二个处理器家族的速度高达3GHz，该处理器家族拥有512KB二级高速缓存和1MB、2MB或4MB的三级高速缓存，使用0.13微米制程制造。在 Terms and Conditions of Sale 中，英特尔明确地声明了对其产品的责任和保证，包括销售和使用中的责任和保证，所有权和知识产权等。同时，英特尔也明确地声明了其产品不适合用于医疗、生命维持或生命支持等应用中。英特尔至强处理器MP的规格升级主要体现在以下几个方面： 1.高速缓存：英特尔至强处理器MP具有1MB的三级高速缓存，能够大幅度提高处理器的性能和效率。 2.微体系结构：基于Intel NetBurst微体系结构，英特尔至强处理器MP具有高性能和低功耗的特点。 3.制程技术：英特尔至强处理器MP使用0.18微米制程和0.13微米制程制造，能够提高处理器的性能和效率。 4.速度：英特尔至强处理器MP的速度从1.40GHz到3GHz，能够满足不同应用场景的需求。英特尔至强处理器MP的规格升级对服务器应用产生了深远的影响，提高了服务器的性能和效率，满足了服务器应用中的需求。在服务器应用中，英特尔至强处理器MP的规格升级能够提高服务器的性能和效率，满足了服务器应用中的需求。同时，英特尔至强处理器MP的规格升级也能够降低服务器的功耗，提高服务器的可靠性和稳定性。英特尔至强处理器MP的规格升级对服务器应用产生了深远的影响，提高了服务器的性能和效率，满足了服务器应用中的需求。

8 64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update

Identification Information

The 64-bit Intel

Xeon

processor MP with 1 MB L2 Cache processor can be identified by the

following values:

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the

CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register

accessible through Boundary Scan.

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the

CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register

accessible through Boundary Scan.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers

after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the AP-485

Intel

Processor Identification and the CPUID Instruction Application Note for further

information on the CPUID instruction.

NOTES:

1. These parts have Tcontrol programmed.

2. These parts are enabled for Intel

Extended Memory 64 Technology.

3. These parts have Thermal Monitor 2 (TM2) feature enabled.

4. These parts are enabled for Enhanced Intel SpeedStep® Technology (EIST).

5. These parts are enabled for Enhanced Halt State (CIE).

Family

Model

1111b 0100b

Identification Information

64-bit Intel

Xeon

processor MP with 1 MB L2 Cache processor

S-Spec

Core

Stepping

CPUID

Core Freq

(GHz)

Data Bus

Freq

(MHz)

Cache

Size

Processor

Package

Revision

Package And Revision Notes

SL84U A-0 0F41h 3.16 667 1 MB 01 604-pin micro-PGA with

42.5 x 42.5 mm

FC-PGA4 package

1,2,4,5

SL84W A-0 0F41h 3.66 667 1 MB 01 1,2,3,4,5

SL8UM B-0 0F49H 3.16 667 1 MB 01 604-pin micro-PGA with

42.5 x 42.5 mm

FC-PGA4 package

1,2,4,5

SL84UN B-0 0F49H 3.66 667 1 MB 01 1,2,3,4,5

64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update 9

Identification Information

Mixed Steppings in MP Systems

Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with up to

1 MB L2 cache system bus. The following list and processor matrix describes the requirements to

support mixed steppings:

• Mixed steppings are only supported with processors that have identical family numbers as

indicated by the CPUID instruction.

• While Intel has done nothing to specifically prevent processors operating at differing

frequencies from functioning within a multiprocessor system, there may be uncharacterized

errata that exist in such configurations. Intel does not support such configurations. In mixed

stepping systems, all processors must operate at identical frequencies (i.e., the highest

frequency rating commonly supported by all processors).

• While there are no known issues associated with the mixing of processors with differing cache

sizes in a multiprocessor system, and Intel has done nothing to specifically prevent such

system configurations from operating, Intel does not support such configurations since there

may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of

the same cache size.

• While Intel believes that certain customers may wish to perform validation of system

configurations with mixed frequency or cache sizes, or voltages and that those efforts are an

acceptable option to our customers, customers would be fully responsible for the validation of

such configurations.

• Intel requires that the proper microcode update be loaded on each processor operating in a

multiprocessor system. Any processor that does not have the proper microcode update loaded

is considered by Intel to be operating out of specification.

• The workarounds identified in this and following specification updates must be properly

applied to each processor in the system. Certain errata are specific to the multiprocessor

environment. Errata for all processor steppings will affect system performance if not properly

worked around.

• In mixed stepping systems, the processor with the lowest feature-set, as determined by the

CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in

feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest

stepping as determined by the CPUID instruction.

• While there are no known issues associated with the mixing of processors with differing

voltages in a multiprocessor system, and Intel has done nothing to specifically prevent such

system configurations from operating, Intel does not support such configurations since there

may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of

the same voltage.l

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