Intel 64位至强处理器MP：1MB二级缓存技术规格

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"二级缓存为1MB的英特尔64位至强处理器MP是一款基于Intel NetBurst微架构的服务器级处理器。这款处理器家族包括两种不同的型号，分别采用0.18微米和0.13微米制程技术。早期的型号运行速度在1.40GHz至1.60GHz之间，配备256KB二级缓存和512KB或1MB的三级高速缓存。而较新的型号则可以达到3GHz的时钟频率，具有512KB二级缓存以及1MB、2MB或4MB的三级高速缓存。这些处理器都是为满足高性能计算和多处理器系统的需求而设计的，特别适用于服务器和数据中心环境。" 本文档详细介绍了64位Intel Xeon Processor MP，它具有1MB的二级缓存，是针对多处理器系统优化的一款高性能处理器。文档日期为2005年3月，编号为306751-001，涵盖了关于该处理器的技术规格、性能特征和使用注意事项。 Intel Xeon Processor MP的设计考虑了64位运算能力，这使得它能够处理更大的数据量，提高了处理复杂任务的能力，特别是对于数据库管理、虚拟化、科学计算等应用。1MB的二级缓存在这种处理器中起着关键作用，它能存储更多最近使用的指令和数据，减少对主内存的访问，从而提高整体系统性能。文档还强调，尽管Intel提供这些产品信息，但并未授予任何知识产权许可，用户需根据Intel的产品销售条款和条件使用产品。Intel不承担任何明示或暗示的保修责任，包括但不限于针对特定用途的适用性、商品质量和侵犯任何专利、版权或其他知识产权的保修。同时，Intel保留对规格和产品描述进行更改而不事先通知的权利，设计者不应依赖于任何标记为“保留”或“未定义”的功能或指令。此外，Intel明确指出其产品并不适用于医疗、生命维持或生命安全的应用，因为这些领域要求极高的可靠性和安全性，而Intel的产品可能无法满足这些特殊要求。任何使用Intel产品的设计者和开发者应自行承担风险，并确保其设计符合所有相关的安全和合规标准。

Electrical Specifications

16 64-bit Intel

Xeon™ Processor MP with 1MB L2 Cache Datasheet

2.1.1 Front Side Bus Clock Select (BSEL[1:0])

The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-2 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All processors must operate at the same FSB frequency.

The 64-bit Intel

Xeon™ processor MP with 1MB L2 cache operates at a 667 MHz FSB frequency

(selected by a 166 MHz BCLK[1:0] frequency).

For more information about these pins, refer to Section 6.1 and the appropriate platform design

guide.

2.1.2 Phase Lock Loop (PLL) Power and Filter

CCA

, V

CCIOPLL

are power sources required by the PLL clock generators on the 64-bit Intel

Xeon™ processor MP with 1MB L2 cache. These are analog PLLs and they require low noise

power supplies for minimum jitter. These supplies must be low pass filtered from V

The AC low-pass requirements, with input at V

, are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-1. For recommendations on implementing the

filter, refer to the appropriate platform design guide.

Table 2-2. BSEL[1:0] Frequency Table for BCLK[1:0

BSEL1 BSEL0 Function

0 0 RESERVED

0 1 RESERVED

1 0 RESERVED

1 1 166 MHz

Electrical Specifications

64-bit Intel

Xeon™ Processor MP with 1MB L2 Cache Datasheet 17

NOTES:

1. Diagram not to scale.

2. No specification for frequencies beyond f

core

(core frequency).

3. f

peak

, if existent, should be less than 0.05 MHz.

2.2 Voltage Identification (VID)

The VID[5:0] pins supply the encodings that determine the voltage to be supplied by the V

(the

core voltage for the 64-bit Intel

Xeon™ processor MP with 1MB L2 cache) voltage regulator.

The VID specification for the 64-bit Intel

Xeon™ processor MP with 1MB L2 cache is defined

by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2

Design Guidelines. The voltage set by the VID pins is the maximum V

voltage allowed by the

processor. A minimum V

voltage is provided in Table 2-7 and changes with frequency. This

allows processors running at a higher frequency to have a relaxed minimum V

voltage

specification. The specifications have been set such that one voltage regulator can work with all

supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same core speed may have different default VID settings. Furthermore, any 64-bit Intel

Xeon™ processor MP with 1MB L2 cache, even those on the same processor FSB, can drive

different VID settings during normal operation.

The 64-bit Intel

Xeon™ processor MP with 1MB L2 cache uses six voltage identification pins

(VID[5:0]) to support automatic selection of power supply voltages. Table 2-3 specifies the voltage

level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a

‘0’ refers to a low voltage level. If the processor socket is empty (i.e. when the voltage regulator

sees VID[5:0] = 111111 or VID[5:0] = 011111), or the voltage regulation circuit cannot supply the

voltage that is requested, the processor’s voltage regulator must disable itself. See the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design

Guidelines for more details.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

0 dB

-28 dB

-34 dB

0.2 dB

forbidden

zone

-0.5 dB

forbidden

zone

1 MHz 66 MHz

core

peak1 HzDC

passband

high frequency

band

Electrical Specifications

64-bit Intel

Xeon™ Processor MP with 1MB L2 Cache Datasheet 19

2.3 Reserved, Unused, and TESTHI Pins

All RESERVED pins must be left unconnected. Connection of these pins to V

, V

, or to any

other signal (including each other) can result in component malfunction or incompatibility with

future processors. See Section 5 for a pin listing for the processor and the location of all

RESERVED pins.

For reliable operation, always terminate unused inputs or bidirectional signals to their respective

deasserted states. On-die termination has been included on the 64-bit Intel

Xeon™ processor MP

with 1MB L2 cache to allow signals to be terminated within the processor silicon. Most unused

AGTL+ inputs may be left as no-connects since AGTL+ termination is provided on the processor

silicon. See Table 2-5 for details on AGTL+ signals that do not include on-die termination. Unused

active-high inputs should be connected through a resistor to ground (V

). Unused outputs may be

left unconnected. However, this may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional

signals to power or ground. When tying any signal to power or ground, a resistor will also allow for

system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value

as the on-die termination resistors (R

). See Table 2-15.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may

be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated

may interfere with some TAP functions, complicate debug probing, and prevent boundary scan

testing. Signal termination for these signal types is discussed in the appropriate platform design

guidelines.

Don’t Care pins are pins on the processor package that are not connected to the processor die.

These pins can be connected on the motherboard in any way necessary for compatible motherboard

designs to support other processor versions.

The TESTHI pins should be tied to V

using a matched resistor, where a matched resistor has a

resistance value within ±20% of the impedance of the board transmission line traces. For example,

if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required.

The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below.

Please note that utilization of boundary scan test will not be functional if pins are connected

together. A matched resistor should be used for each group:

• TESTHI[3:0]

• TESTHI[6:5]

• TESTHI4 – cannot be grouped with other TESTHI signals

1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250

0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375

1 1 1 1 0 0 1.1500

1 0 1 1 0 0 1.5500

0 1 1 1 0 0 1.1625

0 0 1 1 0 0 1.5625

1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750

0 1 1 0 1 1 1.1875

0 0 1 0 1 1 1.5875

1 1 1 0 1 0 1.2000

1 0 1 0 1 0 1.6000

Table 2-3. Voltage Identification (VID) Definition (Sheet 2 of 2)

VID5 VID4 VID3 VID2 VID1 VID0 VID (V) VID5 VID4 VID3 VID2 VID1 VID0 VID (V)

Electrical Specifications

20 64-bit Intel

Xeon™ Processor MP with 1MB L2 Cache Datasheet

2.4 Mixing Processors

Intel supports and validates multi-processor configurations in which all processors operate with the

same FSB frequency and internal cache sizes. Intel does not support or validate operation of

processors with different cache sizes. Mixing different processor steppings but the same model

(as per the CPUID instruction) is supported.

2.5 Front Side Bus Signal Groups

The FSB signals are grouped by buffer type as listed in Table 2-4. The buffer type indicates which

AC and DC specifications apply to the signals. AGTL+ input signals have differential input buffers

that use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the

AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”

refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

Implementing a source synchronous data bus requires specifying two sets of timing parameters.

One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#,

HIT#, HITM#, etc.). The second set is for the source synchronous signals that are relative to their

respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous

signals are present (A20M#, IGNNE#, etc.) and can become active at any time during the clock

cycle. Table 2-4 identifies signals as common clock, source synchronous, and asynchronous.

Table 2-4. Front Side Bus Pin Groups (Sheet 1 of 2)

Signal Group Type Signals

AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR[3:1]#, DEFER#, RESET#, RS[2:0]#,

RSP#, TRDY#

AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,

BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,

HITM#, LOCK#, MCERR#

AGTL+ Source Synchronous

I/O

Synchronous to associated

strobe

AGTL+ Strobe Input/Output Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

AGTL+ Asynchronous Output Asynchronous FERR#/PBE#, IERR#, PROCHOT#,

GTL+ Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, SMI#, STPCLK#

GTL+ Asynchronous Output Asynchronous THERMTRIP#

TAP Input Synchronous to TCK TCK, TDI, TMS

TAP Input Asynchronous TRST#

TAP Output Synchronous to TCK TDO

Front Side Bus Clock Input Clock BCLK[1:0]

Signals Associated Strobe

REQ[4:0]#,

A[37:36,16:3]#

ADSTB0#

A[39:38,35:17]# ADSTB1#

D[15:0]#, DBI0# DSTBP0#, DSTBN0#

D[31:16]#, DBI1# DSTBP1#, DSTBN1#

D[47:32]#, DBI2# DSTBP2#, DSTBN2#

D[63:48]#, DBI3# DSTBP3#, DSTBN3#

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