MIPS64®架构程序员指南第二卷：深入MIPS64指令集

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《MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set》是一本针对程序开发人员的专业书籍，作为MIPS架构系列中的第二卷，它详细探讨了MIPS64指令集。该文档是MIPS Technologies Inc.于2013年12月发布的修订版5.04，版权归属于2001年至2013年的MIPS Technologies，强调了其专有性和受法律保护的性质。本书的核心内容涵盖了MIPS64架构的深入理解，这是一种扩展了32位MIPS指令集的64位架构，适用于高性能计算和系统级编程。MIPS64提供了更宽的数据处理能力，支持更大地址空间，这对于处理大量数据和执行复杂的系统级任务至关重要。书中可能包含以下知识点： 1. **MIPS64指令集结构**：介绍了MIPS64指令集的特性，如新的寻址模式、寄存器集（如R64系列）、扩展的算术逻辑单元（ALU）和浮点单元（FPU），以及与32位MIPS指令集的区别。 2. **系统架构**：讨论了MIPS64架构如何在硬件层面实现，包括流水线设计、指令并行执行、内存体系结构等，以优化性能。 3. **数据类型和内存管理**：涵盖了64位数据类型的支持，如双精度浮点数（double），以及如何有效地管理和访问大容量地址空间。 4. **编程模型**：解释了如何编写符合MIPS64规范的程序，包括内存对齐、异常处理、寄存器分配策略，以及向32位代码的兼容性考虑。 5. **指令集应用示例**：通过实际的代码示例展示了MIPS64指令在加密、压缩、图形处理等领域的具体用法，帮助读者理解和实践。 6. **安全性与合规性**：强调了版权和法律限制，指出未经许可复制或修改MIPS64指令集信息可能会触犯不公平竞争和版权法规。 7. **开发者工具和调试**：介绍了用于开发、测试和调试MIPS64代码的相关工具和技术，包括编译器、调试器以及性能分析器。《MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set》是一本实用的资源，为程序员提供了解析和利用MIPS64架构进行高效编程的深度指南。对于从事嵌入式系统、高性能计算或系统级编程的工程师来说，这本书是不可或缺的学习资料。

Chapter 1

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set, Revision 5.04 16

About This Book

The MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set comes as part of a multi-vol-

ume set.

• Volume I-A describes conventions used throughout the document set, and provides an introduction to the

MIPS64® Architecture

• Volume I-B describes conventions used throughout the document set, and provides an introduction to the

microMIPS64™ Architecture

• Volume II-A provides detailed descriptions of each instruction in the MIPS64® instruction set

• Volume II-B provides detailed descriptions of each instruction in the microMIPS64™ instruction set

• Volume III describes the MIPS64® and microMIPS64™ Privileged Resource Architecture which deﬁnes and

governs the behavior of the privileged resources included in a MIPS® processor implementation

• Volume IV-a describes the MIPS16e™ Application-Speciﬁc Extension to the MIPS64® Architecture. Beginning

with Release 3 of the Architecture, microMIPS is the preferred solution for smaller code size.

• Volume IV-b describes the MDMX™ Application-Speciﬁc Extension to the MIPS64® Architecture and

microMIPS64™. With Release 5 of the Architecture, MDMX is deprecated. MDMX and MSA can not be imple-

mented at the same time.

• Volume IV-c describes the MIPS-3D® Application-Speciﬁc Extension to the MIPS® Architecture

• Volume IV-d describes the SmartMIPS®Application-Speciﬁc Extension to the MIPS32® Architecture and the

microMIPS32™ Architecture and is not applicable to the MIPS64® document set nor the microMIPS64™ docu-

ment set.

• Volume IV-e describes the MIPS® DSP Module to the MIPS® Architecture

• Volume IV-f describes the MIPS® MT Module to the MIPS® Architecture

• Volume IV-h describes the MIPS® MCU Application-Speciﬁc Extension to the MIPS® Architecture

• Volume IV-i describes the MIPS® Virtualization Module to the MIPS® Architecture

• Volume IV-j describes the MIPS® SIMD Architecture Module to the MIPS® Architecture

1.1 Typographical Conventions

This section describes the use of italic, bold and courier fonts in this book.

About This Book

17 MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set, Revision 5.04

1.1.1 Italic Text

• is used for emphasis

• is used for bits, ﬁelds, registers, that are important from a software perspective (for instance, address bits used by

software, and programmable ﬁelds and registers), and various ﬂoating point instruction formats, such as S, D,

and PS

• is used for the memory access types, such as cached and uncached

1.1.2 Bold Text

• represents a term that is being deﬁned

• is used for bits and ﬁelds that are important from a hardware perspective (for instance, register bits, which are

not programmable but accessible only to hardware)

• is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through

• is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as deﬁned below.

1.1.3 Courier Text

Courier ﬁxed-width font is used for text that is displayed on the screen, and for examples of code and instruction

pseudocode.

1.2 UNPREDICTABLE and UNDEFINED

The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the

processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions

in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register).

Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and

unprivileged software can cause UNPREDICTABLE results or operations.

1.2.1 UNPREDICTABLE

UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction,

or as a function of time on the same implementation or instruction. Software can never depend on results that are

UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is gener-

ated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.

UNPREDICTABLE results or operations have several implementation restrictions:

• Implementations of operations generating UNPREDICTABLE results must not depend on any data source

(memory or internal state) which is inaccessible in the current processor mode

• UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which

is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user

mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in

another process

1.3 Special Symbols in Pseudocode Notation

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set, Revision 5.04 18

• UNPREDICTABLE operations must not halt or hang the processor

1.2.2 UNDEFINED

UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to

instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior

may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED opera-

tions or behavior may cause data loss.

UNDEFINED operations or behavior has one implementation restriction:

• UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which

there is no exit other than powering down the processor). The assertion of any of the reset signals must restore

the processor to an operational state

1.2.3 UNSTABLE

UNSTABLE results or values may vary as a function of time on the same implementation or instruction. Unlike

UNPREDICTABLE values, software may depend on the fact that a sampling of an UNSTABLE value results in a

legal transient value that was correct at some point in time prior to the sampling.

UNSTABLE values have one implementation restriction:

• Implementations of operations generating UNSTABLE results must not depend on any data source (memory or

internal state) which is inaccessible in the current processor mode

1.3 Special Symbols in Pseudocode Notation

In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation

resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1.1.

Table 1.1 Symbols Used in Instruction Operation Statements

Symbol Meaning

← Assignment

=, ≠ Tests for equality and inequality

|| Bit string concatenation

A y-bit string formed by y copies of the single-bit value x

b#n A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the

binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#"

preﬁx is omitted, the default base is 10.

0bn A constant value n in base 2. For instance 0b100 represents the binary value 100 (decimal 4).

0xn A constant value n in base 16. For instance 0x100 represents the hexadecimal value 100 (decimal 256).

y..z

Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is less

than z, this expression is an empty (zero length) bit string.

+, − 2’s complement or ﬂoating point arithmetic: addition, subtraction

About This Book

19 MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set, Revision 5.04

*, × 2’s complement or ﬂoating point multiplication (both used for either)

div 2’s complement integer division

mod 2’s complement modulo

/ Floating point division

< 2’s complement less-than comparison

> 2’s complement greater-than comparison

≤ 2’s complement less-than or equal comparison

≥ 2’s complement greater-than or equal comparison

nor Bitwise logical NOR

xor Bitwise logical XOR

and Bitwise logical AND

or Bitwise logical OR

not Bitwise inversion

&& Logical (non-Bitwise) AND

<< Logical Shift left (shift in zeros at right-hand-side)

>> Logical Shift right (shift in zeros at left-hand-side)

GPRLEN The length in bits (32 or 64) of the CPU general-purpose registers

GPR[x] CPU general-purpose register x. The content of GPR[0] is always zero. In Release 2 of the Architecture,

GPR[x] is a short-hand notation for SGPR[ SRSCtl

CSS

, x].

SGPR[s,x] In Release 2 of the Architecture and subsequent releases, multiple copies of the CPU general-purpose regis-

ters may be implemented. SGPR[s,x] refers to GPR set s, register x.

FPR[x] Floating Point operand register x

FCC[CC] Floating Point condition code CC. FCC[0] has the same value as COC[1].

FPR[x] Floating Point (Coprocessor unit 1), general register x

CPR[z,x,s] Coprocessor unit z, general register x, select s

CP2CPR[x] Coprocessor unit 2, general register x

CCR[z,x] Coprocessor unit z, control register x

CP2CCR[x] Coprocessor unit 2, control register x

COC[z] Coprocessor unit z condition signal

Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number

BigEndianMem Endian mode as conﬁgured at chip reset (0 →Little-Endian, 1 → Big-Endian). Speciﬁes the endianness of

the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endi-

anness of Kernel and Supervisor mode execution.

BigEndianCPU The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, this

endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com-

puted as (BigEndianMem XOR ReverseEndian).

ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only,

and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as

(SR

and User mode).

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

1.3 Special Symbols in Pseudocode Notation

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set, Revision 5.04 20

LLbit Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is

set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation,

when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc-

tions.

I:,

I+n:,

I-n:

This occurs as a preﬁx to Operation description lines and functions as a label. It indicates the instruction

time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current

instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a

time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the

instruction time of another instruction. When this happens, the instruction operation is written in sections

labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode

appears to occur. For example, an instruction may have a result that is not available until after the next

instruction. Such an instruction has the portion of the instruction operation description that writes the result

The effect of pseudocode statements for the current instruction labelled I+1 appears to occur “at the same

time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode

sequence, the effects of the statements take place in order. However, between sequences of statements for

different instructions that occur “at the same time,” there is no deﬁned order. Programs must not depend on a

particular order of evaluation between such sections.

PC The Program Counter value. During the instruction time of an instruction, this is the address of the instruc-

tion word. The address of the instruction that occurs during the next instruction time is determined by assign-

ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any

pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc-

tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the

instruction time of the instruction in the branch delay slot.

In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the

restart address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register

on an exception. The PC value contains a full 64-bit address all of which are signiﬁcant during a memory ref-

erence.

ISA Mode In processors that implement the MIPS16e Application Speciﬁc Extension or the microMIPS base architec-

tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol-

lows:

In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a

combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link

instruction, or into a Coprocessor 0 register on an exception.

PABITS The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36

physical address bits were implemented, the size of the physical address space would be 2

PABITS

bytes.

SEGBITS The number of virtual address bits implemented in a segment of the address space is represented by the sym-

bol SEGBITS. As such, if 40 virtual address bits are implemented in a segment, the size of the segment is

SEGBITS

= 2

bytes.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

Encoding Meaning

0 The processor is executing 32-bit MIPS instructions

1 The processor is executing MIIPS16e or microMIPS

instructions

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MIPS64®架构程序员指南第二卷：深入MIPS64指令集

MIPS64架构入门：程序员指南

MIPS32架构指南：指令集详解

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MIPS® Architecture For Programmers Volume III

MIPS® Architecture For Programmers

MIPS32 Architecture for Programmers Volume IV-d

MIPS64® Architecture For Programmers, Vol 1: Introduction to the MIPS64®

The MIPS32® Architecture For Programmers(英文，三卷全)

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