UDA1341TS音频编解码器芯片详细规格

uda1341ts

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"uda1341ts 芯片手册" uda1341TS是一款由Philips Semiconductors（现NXP Semiconductors）设计的经济型音频编解码器，专用于MiniDisc (MD) 家庭音响和便携式应用。该芯片的手册提供详细的技术规格和功能描述，旨在帮助开发者和工程师更好地理解和使用uda1341TS。 1. 特性 1.1 通用特性：uda1341TS适用于多种音频处理需求，尤其适合MD系统。 1.2 多格式数据接口：支持不同类型的音频数据格式，以适应不同的音源和设备兼容性。 1.3 DAC数字音频处理：内置数字模拟转换器(DAC)，能进行高级的音频信号处理，提高声音质量。 1.4 高级音频配置：允许用户根据需求自定义音频设置，以优化系统性能。 2. 一般描述该芯片是一个集成的音频解决方案，集成了模数转换器(ADC)和数模转换器(DAC)，同时具备多种音频处理功能。 3. 订购信息提供了uda1341TS芯片的订购细节，包括不同的封装选项和版本。 4. 快速参考数据包含关键参数和性能指标的快速概览，便于工程师快速评估其是否满足项目需求。 5. 布局图展示了芯片内部各个功能模块的布局，帮助理解其工作原理。 6. 引脚配置描述了uda1341TS的引脚分配和功能，对于电路设计至关重要。 7. 功能描述 7.1 系统时钟：提供稳定的时钟信号，确保音频处理的精确性。 7.2 引脚兼容性：确保在不同应用场景中的兼容性。 7.3 模拟前端：接收并处理来自外部的模拟音频信号。 7.4 可编程增益放大器(PGA)：根据需要调整输入信号的增益。 7.5 模数转换器(ADC)：将模拟信号转换为数字信号。 7.6 数字自动增益控制(AGC)：自动调整输入信号的增益，保持恒定的输出水平。 7.7 AGC状态检测：监测AGC的工作状态。 7.8 数字混频器：混合多路音频信号。 7.9 降采样滤波器(ADC)：降低ADC输出的采样率。 7.10 过载检测(ADC)：检测输入信号是否超出范围。 7.11 静音(ADC)：可以对ADC输出进行静音控制。 7.12 插值滤波器(DAC)：提升DAC输出信号的平滑度。 7.13 峰值检测器：检测音频信号的峰值，防止失真。 7.14 快速静音：快速切换到静音模式，减少噪声。 7.15 噪声整形器(DAC)：减少量化噪声，提高音频质量。 7.16 滤流流数字至模拟转换器(FSDAC)：专为改善音频输出而设计。 7.17 多格式输入/输出接口：支持多种音频格式的输入和输出。 7.18 L3接口：可能是指与微控制器或处理器通信的接口，用于控制和配置uda1341TS。 uda1341TS芯片手册提供了全面的技术信息，不仅包括芯片的基本功能，还深入探讨了其在实际应用中的工作原理和配置选项，是开发音频系统尤其是MD相关设备时的重要参考资料。

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2002 May 16 7

Philips Semiconductors Product speciﬁcation

Economy audio CODEC for MiniDisc (MD)

home stereo and portable applications

UDA1341TS

7 FUNCTIONAL DESCRIPTION

7.1 System clock

The UDA1341TS accommodates slave mode only, this

means that in all applications the system devices must

provide the system clock. The system frequency is

selectable. The options are 256f

, 384f

or 512f

The system clock must be locked in frequency to the digital

interface signals.

7.2 Pin compatibility

The UDA1341TS is partially pin compatible with the

UDA1340M and UDA1344TS, making an upgrade of a

printed-circuit board from UDA1340M to UDA1341TS

easier. The pins that are compatible with the UDA1340M

are marked in Fig.3.

7.3 Analog front end

The analog front end of the UDA1341TS consists of two

stereo ADCs with a Programmable Gain Amplifier (PGA)

in channel 2. The PGA is intended to pre-amplify a

microphone signal applied to the input channel 2.

Input channel 1 has a selectable 0 or 6 dB gain stage, to

be controlled via the L3-interface. In this way, input signals

of 1 V (RMS value) or 2 V (RMS value) e.g. from a

CD source can be supported using an external resistor of

12 kΩ in series with the input channel 1. The application

modes are given in Table 1.

Table 1 Application modes using input gain stage

Note

1. If there is no need for 2 V (RMS value) input signal

support, the external resistor should not be used.

7.4 Programmable Gain Ampliﬁer (PGA)

The PGA can be set via the L3-interface at the gain

settings: −3, 0, 3, 9, 15, 21 or 27 dB.

7.5 Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1341TS consists of two

3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The over-sampling ratio is 128.

7.6 Digital Automatic Gain Control (AGC)

Input channel 2 has a digital AGC to compress the

dynamic range when a microphone signal is applied to

input channel 2. The digital AGC can be switched on and

off via the L3-interface. In the on state the AGC

compresses the dynamic range of the input signal of input

channel 2. Via the L3-interface the user can set the

parameters of the AGC: attack time, decay time and output

level. When the AGC is set off via the L3-interface, the gain

of input channel 2 can be set manually. In this case the

gain of the PGA and digital AGC are combined. The range

of the gain of the input channel 2 is from −3 to +60.5 dB in

steps of 0.5 dB.

7.7 AGC status detection

The AGCSTAT signal from the digital AGC is HIGH when

the gain level of the AGC is below 8 dB. This signal can be

used to give the PGA a new gain setting via the

L3-interface and to power e.g. a LED.

7.8 Digital mixer

The two stereo ADCs (including the AGC) can be used in

four modes:

• ADC1 only mode (for line input); input channel 2 is off

• ADC2 only mode, including PGA and digital AGC (for

microphone input); input channel 1 is off

• ADC1 + ADC2 mixer mode, including PGA and AGC

• ADC1 and ADC2 double differential mode (improved

ADC performance).

Important: In order to prevent crosstalk between the line

inputs no signal should be applied to the microphone input

in the double differential mode.

In all modes (except the double differential mode) a

reference voltage is always present at the input of the

ADC. However, in the double differential mode there is no

reference voltage present at the microphone input.

In the mixer mode, the output signals of both ADCs in

channel 1 and channel 2 (after the digital AGC) can be

mixed with coefficients that can be set via the L3-interface.

The range of the mixer coefficients is from 0 to −∞ dB in

1.5 dB steps.

RESISTOR

(12 kΩ)

INPUT

GAIN

SWITCH

MAXIMUM INPUT VOLTAGE

Present 0 dB 2 V (RMS value) input signal;

note 1

Present 6 dB 1 V (RMS value) input signal

Absent 0 dB 1 V (RMS value) input signal

Absent 6 dB 0.5 V (RMS value) input signal

2002 May 16 8

Philips Semiconductors Product speciﬁcation

Economy audio CODEC for MiniDisc (MD)

home stereo and portable applications

UDA1341TS

7.9 Decimation ﬁlter (ADC)

The decimation from 128f

is performed in two stages.

The first stage realizes 3rd order characteristic,

decimating by 16. The second stage consists of

3 half-band filters, each decimating by a factor of 2.

Table 2 Decimation ﬁlter characteristics

7.10 Overload detection (ADC)

This name is convenient but a little inaccurate. In practice

the output is used to indicate whenever that output data, in

either the left or right channel, is bigger than −1 dB (actual

figure is −1.16 dB) of the maximum possible digital swing.

If this condition is detected the OVERFL output is forced

HIGH for at least 512f

cycles (11.6 ms at f

= 44.1 kHz).

This time-out is reset for each infringement.

7.11 Mute (ADC)

On recovery from power-down or switching on of the

system clock, the serial data output on pin DATAO is held

at LOW level until valid data is available from the

decimation filter. This time depends on whether the

DC-cancellation filter is selected:

• DC cancel off:

; t = 23.2 ms at f

= 44.1 kHz

• DC cancel on:

; t = 279 ms at f

= 44.1 kHz.

7.12 Interpolation ﬁlter (DAC)

The digital filter interpolates from 1f

to 128f

by means of

a cascade of a recursive filter and a Finite Impulse

Response (FIR) filter.

Table 3 Interpolation ﬁlter characteristics

7.13 Peak detector

In the playback path a peak level detector is build in.

The position of the peak detection can be set via the

L3-interface to either before or after the sound features.

The peak level detector is implemented as a peak-hold

detector, which means that the highest sound level is hold

until the peak level is read out via the L3-interface. After

read-out the peak level registers are reset.

7.14 Quick mute

A hard mute can be activated via the static pin QMUTE.

When QMUTE is set HIGH, the output signal is instantly

muted to zero. Setting QMUTE to LOW, the mute is

instantly de-activated.

7.15 Noise shaper (DAC)

The 3rd-order noise shaper operates at 128f

. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique allows for high

signal-to-noise ratios. The noise shaper output is

converted into an analog signal using a filter stream

digital-to-analog converter.

ITEM CONDITIONS

VALUE

(dB)

Passband ripple 0 to 0.45f

±0.05

Stop band >0.55f

−60

Dynamic range 0 to 0.45f

108

Overall gain input channel 1;

0 dB input

−1.16

sin x

------------

1024

-------------

12288

----------------

ITEM CONDITIONS

VALUE

(dB)

Passband ripple 0 to 0.45f

±0.03

Stop band >0.55f

−50

Dynamic range 0 to 0.45f

108

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