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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG8
CFG10
CFG14
CFG15
CFG17
CFG3
CFG4
CFG9
PM_EXTTS#1
PLTRST_R#
EC_EXTTS#0
M_OCDOCMP1
M_OCDOCMP0
M_OCDOCMP0
M_OCDOCMP1
CFG11
CFG6
CFG7
CFG5
CFG12
CFG13
CFG18
CFG16
CFG19
PWROK
H_VREF
M_ODT0
EC_EXTTS#0
M_ODT1
M_ODT2
MCH_CLKSEL0
DDR_CS1_DIMMA#
DMI_RXP3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DMI_RXN2
DMI_RXP2
DMI_TXP2
DMI_TXP3
DMI_TXN3
DMI_RXN3
DMI_TXN2
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
CLK_MCH_3GPLL
CLK_MCH_3GPLL#M_CLK_DDR0
M_CLK_DDR3
M_CLK_DDR2
M_CLK_DDR1
DMI_RXP1
CFG20
DMI_RXP0
DMI_RXN0
DMI_RXN1
DREFCLK#
DMI_TXP0
DMI_TXP1
DREFCLK
SMRCOMPP
SMRCOMPN
DMI_TXN0
DREF_SSCLK#
DMI_TXN1
DREF_SSCLK
MCH_CLKSEL1
MCH_CLKSEL2
DDR_CS0_DIMMA#
PM_BMBUSY#
H_THERMTRIP#
CLKREQC#
PM_EXTTS#1
V_DDR_MCH_REF
M_ODT3
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
H_RS#2
H_D#50
H_D#45
H_D#11
H_ADS#
H_DSTBP#0
H_DSTBN#1
CLK_MCH_BCLK
H_ADSTB#0
H_A#14
H_A#8
H_D#47
H_D#12
H_TRDY#
H_REQ#4
H_A#27
H_A#11
H_D#39
H_D#26
H_D#24
H_D#6
H_D#0
H_SWNG0
H_DRDY#
H_A#28
H_A#24
H_A#21
H_SWNG1
H_D#57
H_D#43
H_D#18
H_HIT#
H_A#19
H_D#52
H_D#21
H_D#15
H_DSTBP#3
H_REQ#0
H_A#17
H_A#3
H_D#46
H_D#38
H_HITM#
H_DINV#1
H_A#25
H_A#6
H_D#58
H_D#30
H_D#17
H_D#5
H_DEFER#
H_DINV#3
H_ADSTB#1
H_A#31
H_A#29
H_XSCOMP
H_D#61
H_D#33
H_D#29
H_D#20
H_DINV#2
H_A#22
H_D#51
H_D#48
H_D#40
H_D#19
H_D#8
H_D#4
H_VREF
H_RS#0
H_A#26
H_A#7
H_D#53
H_CPUSLP#
H_DBSY#
H_BR0#
H_DSTBN#2
H_DINV#0
H_A#23
H_A#12
H_A#5
H_D#60
H_D#44
H_D#25
H_D#16
H_BPRI#
H_DSTBN#3
H_REQ#1
H_A#13
H_D#59
H_D#41
H_D#37
H_D#28
H_D#27
H_D#23
H_D#9
H_D#1
H_RESET#
H_A#20
H_A#15
H_D#54
H_D#42
H_D#36
H_D#14
H_D#3
H_RS#1
H_A#9
H_A#4
H_D#56
H_D#55
H_D#34
H_D#13
H_SWNG1
H_LOCK#
H_DSTBP#2
H_DSTBP#1
H_DSTBN#0
H_REQ#3
H_D#63
H_D#22
H_D#10
H_BNR#
H_REQ#2
H_A#16
H_SWNG0
H_YSCOMP
H_YRCOMP
H_XRCOMP
H_D#35
H_D#31
H_D#7
H_DPWR#
CLK_MCH_BCLK#
H_A#30
H_A#18
H_A#10
H_D#62
H_D#49
H_D#32
H_D#2
VREF
VREF
V_DDR_MCH_REF
V_DDR_MCH_REF
+VCCP
+VCCP+VCCP
+VCCP
+3VS
+1.8V
+1.8V
+5VALW
+1.8V
H_D#[0..63]<6>
H_A#[3..31] <6>
H_REQ#[0..4] <6>
H_DSTBN#[0..3] <6>
H_DSTBP#[0..3] <6>
H_RS#[0..2] <6>
DMI_TXN0<22>
DMI_TXN1<22>
DMI_TXN2<22>
DMI_TXN3<22>
DMI_TXP0<22>
DMI_TXP1<22>
DMI_TXP2<22>
DMI_TXP3<22>
DMI_RXN0<22>
DMI_RXN1<22>
DMI_RXN2<22>
DMI_RXN3<22>
DMI_RXP0<22>
DMI_RXP1<22>
DMI_RXP2<22>
DMI_RXP3<22>
M_CLK_DDR0<15>
M_CLK_DDR1<15>
M_CLK_DDR2<16>
M_CLK_DDR3<16>
M_CLK_DDR#0<15>
M_CLK_DDR#1<15>
M_CLK_DDR#2<16>
M_CLK_DDR#3<16>
DDR_CS0_DIMMA#<15>
DDR_CS1_DIMMA#<15>
PM_BMBUSY#<22>
H_DPRSLPVR<22,46>
H_THERMTRIP#<6,21>
CLKREQC# <5>
CLK_MCH_3GPLL# <5>
CLK_MCH_3GPLL <5>
CFG20 <13>
CFG19 <13>
CFG18 <13>
CFG16 <13>
CFG13 <13>
CFG12 <13>
CFG9 <13>
CFG7 <13>
CFG5 <13>
MCH_CLKSEL2 <5>
MCH_CLKSEL1 <5>
MCH_CLKSEL0 <5>
EC_EXTTS#0<15,16,33>
DREFCLK# <5>
DREFCLK <5>
DREF_SSCLK# <5>
DREF_SSCLK <5>
PWROK<22,33,34>
MCH_ICH_SYNC#<20>
V_DDR_MCH_REF<15,16>
M_ODT0<15>
M_ODT1<15>
M_ODT2<16>
M_ODT3<16>
DDR_CKE0_DIMMA<15>
DDR_CKE1_DIMMA<15>
PLT_RST#<18,20,22,24,28,32,33,35>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>
H_LOCK# <6>
H_BPRI# <6>
H_DINV#3 <6>
H_DPWR# <6>
CLK_MCH_BCLK <5>
H_HIT# <6>
H_DINV#2 <6>
H_BNR# <6>
H_DINV#0 <6>
H_TRDY# <6>
H_HITM# <6>
H_ADSTB#1 <6>
H_CPUSLP# <6,21>
H_ADS# <6>
H_DEFER# <6>
H_BR0# <6>
H_DBSY# <6>
H_ADSTB#0 <6>
H_DINV#1 <6>
H_RESET# <6>
CLK_MCH_BCLK# <5>
H_DRDY# <6>
Title
Size Document Number Rev
Date: Sheet
of
Compal Electronics, Inc.(KunShan)
Custom
PecosII-IDX80-LA3291
X 0.5
Calistoga1/6-GTL/DMIDDRMUX
953Monday, January 08, 2007
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.
Stuff R546 & R547 for A1 Calistoga
Description at page13.
Layout Note:
Route as short
as possible
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
Use +1.8V divide voltage for V_DDR_MCH_REF, R545/R548 use 100_0402_1%
Use buffer to generate V_DDR_MCH_REF, R545/R548 use 1K_0402_1%
T6
PAD
T5
PAD
T4
PAD
C455
0.1U_0402_16V4Z
1
2
DMI
DDR MUXING
CFG
PM
CLKNC
RESERVED
U3B
CALISTOGA_FCBGA1466~D
DMIRXN0
AE35
DMIRXN1
AF39
DMIRXN2
AG35
DMIRXN3
AH39
DMIRXP0
AC35
DMIRXP1
AE39
DMIRXP2
AF35
DMIRXP3
AG39
DMITXN0
AE37
DMITXN1
AF41
DMITXN2
AG37
DMITXN3
AH41
DMITXP0
AC37
DMITXP1
AE41
DMITXP2
AF37
DMITXP3
AG41
SM_CK0
AY35
SM_CK1
AR1
SM_CK2
AW7
SM_CK3
AW40
SM_CK0#
AW35
SM_CK1#
AT1
SM_CK2#
AY7
SM_CK3#
AY40
SM_OCDCOMP0
AL20
SM_OCDCOMP1
AF10
SM_ODT0
BA13
SM_ODT1
BA12
SM_ODT2
AY20
SM_ODT3
AU21
SM_RCOMPN
AV9
SM_RCOMPP
AT9
SM_VREF0
AK1
SM_VREF1
AK41
SM_CKE0
AU20
SM_CKE1
AT20
SM_CKE2
BA29
SM_CKE3
AY29
SM_CS0#
AW13
SM_CS1#
AW12
SM_CS2#
AY21
SM_CS3#
AW21
CFG16
G18
CFG1
K18
CFG2
J18
CFG3
F18
CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG0
K16
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
G_CLKP
AG33
G_CLKN
AF33
D_REF_CLKN
A27
D_REF_CLKP
A26
D_REF_SSCLKN
C40
D_REF_SSCLKP
D41
NC0
A3
NC1
A39
NC2
A4
NC3
A40
NC4
AW1
NC5
AW41
NC6
AY1
NC7
BA1
NC8
BA2
NC9
BA3
NC10
BA39
NC11
BA40
NC12
BA41
NC13
C1
NC14
AY41
NC15
B2
NC16
B41
NC17
C41
NC18
D1
PM_BMBUSY#
G28
PM_EXTTS0#
F25
PM_EXTTS1#
H26
PM_THERMTRIP#
G6
PWROK
AH33
RSTIN#
AH34
RESERVED1
T32
RESERVED2
R32
RESERVED3
F3
RESERVED4
F7
RESERVED5
AG11
RESERVED6
AF11
RESERVED7
H7
RESERVED8
J19
RESERVED9
A41
RESERVED10
A34
RESERVED11
D28
RESERVED12
D27
RESERVED13
A35
ICH_SYNC#
K28
CLK_REQ#
H32
U1
G2992F1U_SO8
Buffer@
VOUT
4
NC
5
GND
2
VREF
3
VIN
1
VCNTL
6
NC
7
NC
8
TP
9
R537 80.6_0402_1%
1 2
C680
1U_0603_10V4Z
Buffer@
1
2
HOST
U3A
CALISTOGA_FCBGA1466~D
HD0#
F1
HD1#
J1
HD2#
H1
HD3#
J6
HD4#
H3
HD5#
K2
HD6#
G1
HD7#
G2
HD8#
K9
HD9#
K1
HD10#
K7
HD11#
J8
HD12#
H4
HD13#
J3
HD14#
K11
HD15#
G4
HD16#
T10
HD17#
W11
HD18#
T3
HD19#
U7
HD20#
U9
HD21#
U11
HD22#
T11
HD23#
W9
HD24#
T1
HD25#
T8
HD26#
T4
HD27#
W7
HD28#
U5
HD29#
T9
HD30#
W6
HD31#
T5
HD32#
AB7
HD33#
AA9
HD34#
W4
HD35#
W3
HD36#
Y3
HD37#
Y7
HD38#
W5
HD39#
Y10
HD40#
AB8
HD41#
W2
HD42#
AA4
HD43#
AA7
HD44#
AA2
HD45#
AA6
HD46#
AA10
HD47#
Y8
HD48#
AA1
HD49#
AB4
HD50#
AC9
HD51#
AB11
HD52#
AC11
HD53#
AB3
HD54#
AC2
HD55#
AD1
HD56#
AD9
HD57#
AC1
HD58#
AD7
HD59#
AC6
HD60#
AB5
HD61#
AD10
HD62#
AD4
HD63#
AC8
HVREF1
K13
HXRCOMP
E1
HXSCOMP
E2
HYRCOMP
Y1
HYSCOMP
U1
HXSWING
E4
HYSWING
W1
HA3#
H9
HA4#
C9
HA5#
E11
HA6#
G11
HA7#
F11
HA8#
G12
HA9#
F9
HA10#
H11
HA11#
J12
HA12#
G14
HA13#
D9
HA14#
J14
HA15#
H13
HA16#
J15
HA17#
F14
HA18#
D12
HA19#
A11
HA20#
C11
HA21#
A12
HA22#
A13
HA23#
E13
HA24#
G13
HA25#
F12
HA26#
B12
HA27#
B14
HA28#
C12
HA29#
A14
HA30#
C14
HA31#
D14
HREQ#0
D8
HREQ#1
G8
HREQ#2
B8
HREQ#3
F8
HREQ#4
A8
HADSTB#0
B9
HADSTB#1
C13
HRS0#
B4
HRS1#
E6
HRS2#
D6
HCLKN
AG1
HCLKP
AG2
HDINV#0
J7
HDINV#1
W8
HDINV#2
U3
HDINV#3
AB10
HDSTBN#0
K4
HDSTBN#1
T7
HDSTBN#2
Y5
HDSTBN#3
AC4
HDSTBP#0
K3
HDSTBP#1
T6
HDSTBP#2
AA5
HDSTBP#3
AC5
HCPURST#
B7
HADS#
E8
HTRDY#
E7
HDPWR#
J9
HDRDY#
H8
HDEFER#
C3
HHITM#
D4
HHIT#
D3
HLOCK#
B3
HBREQ0#
C7
HBNR#
C6
HBPRI#
F6
HDBSY#
A7
HCPUSLP#
E3
HVREF0
J13
T3
PAD
R546
40.2_0402_1% @
12
R556
200_0402_1%
12
R539
54.9_0402_1%
12
R446
0_0805_5%
1.8_divider@
1 2
R549
221_0603_1%
12
R542 100_0402_1%
12
T9
PAD
R545
1K_0402_1%
12
R553
10K_0402_5%@
12
T8
PAD
R555
100_0402_1%
12
C456
0.1U_0402_16V4Z
1
2
R551
100_0402_1%
12
T1
PAD
C457
0.1U_0402_16V4Z
1
2
R540
54.9_0402_1%
12
R541 0_0402_5%
1 2
T2
PAD
R547
40.2_0402_1% @
12
R538
80.6_0402_1%
1 2
R550
221_0603_1%
12
R554
100_0402_1%
12
T7
PAD
R548
1K_0402_1%
12
R552
10K_0402_5%
12
C454
0.1U_0402_16V4Z
1
2
C932
10U_1206_6.3V7K
Buffer@
1
2
R543
24.9_0402_1%
12
R544
24.9_0402_1%
12
C931
10U_1206_6.3V7K
Buffer@
1
2