Lattice MachXO2™ FPGA: Ultra Low Power Features and On-Chip Memory

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“FPGA lattice MachXO2™ Family Data Sheet.pdf” MachXO2™是Lattice Semiconductor公司推出的一款现场可编程门阵列（FPGA），它以其灵活性、低功耗特性以及丰富的内置功能而受到关注。这款器件的数据手册（Data Sheet）详细介绍了其主要特性、性能指标和应用领域。 MachXO2™家族提供了六种不同规模的设备，从256个LUT4（查找表）到6864个LUT4，以及19至335个输入/输出（I/O）引脚，满足了不同设计需求的范围。LUT4是FPGA的基本构建单元，可以配置实现各种逻辑功能。在功耗方面，MachXO2™采用了先进的65nm低功耗工艺技术，使得待机功率低至19微瓦。此外，它还支持可编程的低摆幅差分I/O，这有助于降低功耗并提高信号完整性。设备内还包含了多种节能选项，如待机模式，以适应不同应用场景。在内存资源上，MachXO2™集成了嵌入式和分布式内存。最高可提供240K比特的sysMEM™嵌入式块RAM和54K比特的分布式RAM，这在需要快速访问和临时存储数据的应用中非常有用。此外，专用的FIFO（先进先出）控制逻辑使得数据传输更加高效。 MachXO2™还包括了片上用户闪存（User Flash Memory），容量高达256K比特，具有100,000次写周期的耐久性。用户可以通过WISHBONE、SPI、I2C和JTAG接口访问这个闪存。这使得MachXO2™能够作为软处理器的程序存储器或者独立的闪存设备使用。在接口支持上，MachXO2™预设了源同步I/O（Source Synchronous I/O）功能，例如DDR（双倍数据速率）寄存器，这对于高速数据传输和与外部存储器的接口设计来说至关重要。 MachXO2™ FPGA因其广泛的逻辑资源、低功耗设计、丰富的内存选项和灵活的接口特性，成为各种嵌入式系统、工业控制、通信以及其他需要定制化逻辑解决方案的领域的理想选择。设计者可以根据具体应用选择不同规模的器件，并利用其强大的配置能力来优化电路性能和功耗。

2-12

Architecture

MachXO2 Family Data Sheet

Figure 2-8. sysMEM Memory Primitives

Table 2-6. EBR Signal Descriptions

Port Name Description Active State

CLK Clock Rising Clock Edge

CE Clock Enable Active High

OCE

Output Clock Enable Active High

RST Reset Active High

Byte Enable Active High

WE Write Enable Active High

AD Address Bus —

DI Data In —

DO Data Out —

CS Chip Select Active High

AFF FIFO RAM Almost Full Flag —

FF FIFO RAM Full Flag —

AEF FIFO RAM Almost Empty Flag —

EF FIFO RAM Empty Flag —

RPRST FIFO RAM Read Pointer Reset —

1. Optional signals.

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-

tively.

4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the

read port chip select, ORE is the output read enable.

DI[17:0]

CLKW

FIFO RAM

DO[17:0]

RST

FULLI

AFF

AEF

CLKR

CSR[1:0]

ORE

RPRST

CSW[1:0]

EMPTYI

ROM

DO[17:0]

AD[12:0]

CLK

RST

CS[2:0]

OCE

EBR EBR

AD[12:0]

DI[8:0]

DO[8:0]

CLK

RST

CS[2:0]

OCE

Single-Port RAM

ADA[12:0]

DIA[8:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[8:0]

OCEA

ADB[12:0]

DI[8:0]

CLKB

CEB

RSTB

WEB

CSB[2:0]

DOB[8:0]

OCEB

True Dual Port RAM

ADW[8:0]

DI[17:0]

CLKW

CEW

RST

CSW[2:0]

ADR[12:0]

CLKR

CER

DO[17:0]

CSR[2:0]

OCER

BE[1:0]

Pseudo Dual Port RAM

EBREBREBR

2-13

Architecture

MachXO2 Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for

all data widths.

3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO Configuration

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is

in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from

the FIFO.

Memory Core Reset

The memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-

chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with

port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and

associated resets for both ports are as shown in Figure 2-9.

Flag Name Programming Range

Full (FF) 1 to max (up to 2

-1)

Almost Full (AF) 1 to Full-1

Almost Empty (AE) 1 to Full-1

Empty (EF) 0

N = Address bit width.

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