LMX2571：低功耗高性能PLL RF合成功放，FSK调制

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LMX2571是一款专为低功耗和高性能设计的PLLatinum RF合成器，它采用FSK调制技术，适用于需要宽频带通信应用。这款集成式芯片的主要特点包括： 1. **频率范围**：LMX2571支持从10MHz到1344MHz的输出频率，提供了极宽的频率覆盖，满足了不同通信系统的调制需求。 2. **高性能VCO**：内置多核压控振荡器(VCO)具备高工作频率，可达5.376GHz，具有出色的相位噪声和杂散抑制能力，例如在480MHz时，12.5kHz偏移的相位噪声为–123dBc/Hz，1MHz偏移为–145dBc/Hz，保证了信号的稳定性和清晰度。 3. **FastLock技术**：通过集成的新型FastLock功能，可以显著缩短锁定时间，提高系统的启动速度和稳定性，这对于实时通信系统至关重要。 4. **整数边界毛刺去除**：为了优化信号质量，LMX2571采用了独特的可编程乘法器，能够有效地处理毛刺问题，即使在毛刺出现在整数边界，也能保证系统的正常工作。 5. **电源管理与接口**：集成5V电荷泵和输出驱动器支持外部压控振荡器，同时提供了专门的5V充电泵和输出分压器，以实现低功耗下的灵活供电。此外，芯片还支持SPI接口，便于外部控制和配置。 6. **锁相环特性**：标准的锁相环(PLL)噪声底限达到–231dBc/Hz，杂散干扰抑制能力超过–75dBc/Hz，确保了信号的纯净度和抗干扰能力。 7. **适用性**：LMX2571既可以直接使用内部VCO，也可以与外部VCO配合使用，为用户提供更大的灵活性。 8. **电源电压兼容性**：支持3.3V和5V电源输入，适合各种微控制器或数字信号处理器(SoC/DSP)环境。 9. **封装选项**：产品提供不同的封装形式，以便于集成到各种电路板设计中。在使用LMX2571时，用户应仔细阅读芯片手册，了解其各项功能、引脚功能和操作注意事项，以充分利用其性能并避免潜在问题。这款芯片对于需要高性能和低功耗无线通信解决方案的工程师来说，是一个理想的选择。

Fast

lock

Int. charge

pump

5V charge

pump

R-divider

Phase

detector

µWIRE

Prescaler

N-divider

Output

divider

Output

divider

G4

modulator

Transmit / Receive

RFoutRx

RFoutTx

Fin

CPout

CPoutExtFLout

OSCin

SPI CEFSK

MUX

TrCtl

VCO

MUX

Power

supply

Lock

dect

MUXout

5V CP

supply

Vcc3p3

VccIO

VcpExt

Enable

LMX2571

ZHCSDH8 –MARCH 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The LMX2571 is a frequency synthesizer with low-noise, high-performance integrated VCOs. The 5-GHz VCO

cores, together with the output channel dividers, can produce frequencies from 10 MHz to 1344 MHz. The

LMX2571 supports two operation modes, synthesizer mode and PLL mode. In synthesizer mode, the entire

device is utilized; in PLL mode the internal VCO is bypassed, and an external VCO is required to implement a

complete synthesizer.

The reference clock input supports a crystal used for the on-chip oscillator, AC-coupled differential clock signals,

and DC-coupled single-ended clock signals such as XO or CMOS clock devices.

The PLL is a fractional-N PLL with programmable Delta Sigma modulator (first order to fourth order). The

fractional denominator is of variable length and up to 24-bits long, providing a frequency step with very fine

resolution.

The internal VCO can be bypassed, allowing the use of an external VCO. A separate 5-V charge pump is

dedicated for the external VCO, eliminating the need for an op-amp to support 5-V VCOs. A new advanced

FastLock technique is developed to shorten the lock time to less than 1.5 ms, even there is a very narrow loop

bandwidth.

A unique programmable multiplier is incorporated in the R-divider. The multiplier is used to avoid and reduce

integer boundary spurs or to increase the phase detector frequency for higher performance.

The LMX2571 supports direct digital FSK modulation, thus allowing a change in the output frequency by

changing the N-divider value. The N-divider value can be programmed through MICROWIRE interface or through

pins. Discrete 2-, 4- and 8-level FSK, as well as arbitrary-level FSK, are supported. Arbitrary-level FSK can be

used to construct pulse-shaping FSK or analog-FM modulation.

The output has an integrated T/R switch, and the divided-down internal or external VCO signal can be output to

either the TX port or the RX port. The switch can also be configured as a 1:2 fanout buffer, providing the signal

on both outputs at the same time. In addition to port switching, the output frequency can be switched between

two pre-defined frequencies, F1 and F2, simultaneously. This feature is ideal for use in FDD duplex system

where the TX frequency is different from RX (LO) frequency.

The LMX2571 requires only a single 3.3-V power supply. Digital logic interface is 1.8-V input compatible. The

analog blocks power supplies use integrated LDOs, eliminating the need for high performance external LDOs.

Programming of the device is achieved through the MICROWIRE interface. The device can be powered down

through a register programming or toggling the Chip Enable (CE) pin.

7.2 Functional Block Diagram

Pre-

divider

MULT

Post-

divider

OSCin Phase detector

LMX2571

www.ti.com.cn

ZHCSDH8 –MARCH 2015

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin and OSCin* pins are used as frequency reference inputs to the device. The OSCin pin can be driven

single-ended with a CMOS clock or a crystal oscillator. The on-chip crystal oscillator can also be used with an

external crystal as the reference clock. Differential clock input is also supported, making it easily to interface with

high performance system clock devices such as TI’s LMK series clock devices.

Because the OSCin or OSCin* signal is used as a clock for VCO calibration, a proper signal needs to be applied

at the OSCin and/or OSCin* pin at the time of programming the R0 register. A higher slew rate tends to yield the

best fractional spurs and phase noise, so a square wave signal is best for the OSCin and/or OSCin*pins. If using

a sine wave, higher frequencies tend to yield better phase noise and fractional spurs due to their higher slew

rates.

7.3.2 R-Dividers and Multiplier

The R-divider consists of a Pre-divider, a Multiplier (MULT), and a Post-divider.

Figure 14. R-Divider

Both the Pre- and Post-dividers divide frequency down while the MULT multiplies frequency up. The purpose of

adding a multiplier is to avoid and reduce integer boundary spurs or to increase the phase-detector frequency for

higher performance. See MULT Multiplier for details. The phase detector frequency, f

, is therefore equal to

= (f

OSCin

/ Pre-divider) * (MULT / Post-divider) (1)

When using the Multiplier (MULT > 1), there are some points to remember:

• The Multiplier must be greater than the Pre-divider.

• Crystal mode must be disabled (XTAL_EN=0).

• Using the multiplier may add noise, especially for multiplier values greater than 6.

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-divider and N-divider and generates a correction current

corresponding to the phase error. This charge pump current is programmable to different strengths.

7.3.4 PLL N-Divider and Fractional Circuitry

The total N-divider value is determined by N

integer

+ NUM / DEN. The N-divider includes fractional compensation

and can achieve any fractional denominator (DEN) from 1 to 16,777,215 (2

– 1). The integer portion, N

integer

, is

the whole part of the N-divider value and the fractional portion, N

frac

= NUM / DEN, is the remaining fraction.

integer

, NUM and DEN are programmable.

The order of the delta sigma modulator is also programmable from integer mode to fourth order. There are

several dithering modes that are also programmable. Dithering is used to reduce fractional spurs. In order to

make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

7.3.5 Partially Integrated Loop Filter

The LMX2571 integrates the third and fourth pole of the loop filter. The values for the resistors can be

programmed independently through the MICROWIRE interface. The larger the values of the resistors, the

stronger the attenuation of the internal loop filter. This partially integrated loop filter can only be used in

synthesizer mode.

CHDIV1

4,5,6,7

CHDIV2

1,2,4,8,16,32,64

OP MUX

Int.

VCO

CHDIV3

1,2,3,Y,9,10

Ext.

VCO

OP MUX

Int. charge

pump

CPout

50pF100pF

LMX2571

ZHCSDH8 –MARCH 2015

www.ti.com.cn

Feature Description (continued)

Figure 15. Integrated Loop Filter

7.3.6 Low-Noise, Fully Integrated VCO

The LMX2571 includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. Output of the VCO is fed to a prescaler before going to the N-divider. The prescaler

value is selectable between 2 and 4. In general, prescaler equals 2 will result in better phase noise especially

when the PLL is operated in fractional-N mode. If the prescaler equals 4, however, the device will consume less

current. The VCO frequency is related to the other frequencies and Prescaler as follows:

VCO

= f

* N-divider * Prescaler (2)

In order to reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency

range is divided into several different frequency bands. This creates the need for frequency calibration in order to

determine the correct frequency band given a desired output frequency. The VCO is also calibrated for amplitude

to optimize phase noise. These calibration routines are activated any time that the R0 register is programmed

with the FCAL_EN bit equals one. It is important that a valid OSCin signal must present before VCO calibration

begins.

This device will support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to

re-calibrate the VCO. This is important for continuous operation of the synthesizer under the most extreme

temperature variation.

7.3.7 External VCO Support

The LMX2571 supports an external VCO in PLL mode. In PLL mode, the internal VCO and its associated charge

pump are powered down, and a 5-V charge pump is switched in to support external VCO. No extra external low

noise op-amp is required to support 5-V tuning range VCO. The external VCO output can be obtained directly

from the VCO or from the device’s RF output buffer.

7.3.8 Programmable RF Output Divider

The internal VCO RF output divider consists of two sub-dividers; the total division value is equal to the

multiplication of them. As a result, the minimum division is 4 while the maximum division is 448.

Figure 16. VCO Output Divider

There is only one output divider when external VCO is being used. This divider supports even and odd division,

and its values are programmable between 1 and 10.

7.3.9 Programmable RF Output Buffer

The RF output buffer type is selectable between push-pull and open drain. If open drain buffer is selected,

external pullup to VccIO is required. Regardless of output type, output power can be programmed to various

levels. The RF output buffer can be disabled while still keeping the PLL in lock. See RF Output Buffer Type for

details.

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