Xilinx FPGA平台Flash XL配置与存储设备用户指南

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本资源是Xilinx FPGA平台的《Platform Flash XL配置与存储设备用户指南》（UG438 v3.0），发布日期为2015年8月5日。标题中提及的"PlatformFlashXL Configuration and Storage Device"表明这是一个专注于Xilinx FPGA平台专用的闪存配置和存储设备管理的文档，可能涉及到FPGA的设计、编程、数据存储和系统优化的相关内容。该文档的重要性在于，它提供了一套针对已过时或即将过时的PlatformFlashXL产品（标注为"PRODUCTOBSOLETE/UNDEROBSOLESCENCE"）的配置和存储设备管理方法。用户指南通常包含详细的步骤和说明，帮助工程师们了解如何正确设置和维护FPGA的闪存，以确保其高效运行和兼容性。文档内容涵盖了以下关键知识点： 1. **配置和存储设备概述**：解释了为何PlatformFlashXL在特定时间被认为是过时的，以及它在FPGA平台中的功能和作用，如配置文件的加载、存储和更新。 2. **配置过程**：介绍了如何通过硬件或软件工具对PlatformFlashXL进行初始化、编程和验证，可能包括使用Xilinx提供的专用工具或者第三方接口。 3. **存储设备管理**：涉及闪存的容量、组织结构、数据备份和恢复策略，以及如何处理不同类型的存储错误和故障。 4. **安全性和隐私**：强调了在使用过程中保护知识产权和敏感数据的重要性，可能包括密码保护、权限管理和加密技术。 5. **免责声明**：明确指出提供的材料"AS IS"，即不保证任何质量或适合特定用途，且Xilinx不对因使用这些材料导致的任何损失或损害承担责任。这意味着用户需要自行承担风险，并可能需要查阅最新的技术文档以适应不断变化的产品规格。 6. **法律责任**：界定了Xilinx的法律责任范围，表明他们仅在法律允许的范围内对材料提供有限支持，不包括合同责任、侵权责任或其他理论下的损失赔偿。阅读和遵循这份指南对于仍在使用PlatformFlashXL的Xilinx FPGA用户来说至关重要，因为它提供了在设备生命周期内的配置和存储设备管理的最佳实践，以及应对可能的技术变迁和兼容性问题的指导。由于该文档的时效性，用户需确保其内容适用于当前版本的FPGA和配套硬件，可能需要结合最新版本的Xilinx支持文档进行参考。

Platform Flash XL Configuration & Storage Device www.xilinx.com 13

UG438 (v3.0) August 5, 2015

Family Description

— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —

board design. When the device signals a ready status after power-on, the device can

immediately burst the FPGA design bitstream (.bit) file to the FPGA. The configuration

performance of Platform Flash XL is ideal for PCI Express end-points and other

high-performance applications (see Chapter 2, “High-Speed Configuration”). Platform

Flash XL is optimized for the FPGA Slave SelectMAP configuration mode, but it also

supports Master SelectMAP and Master BPI-Up modes (see Chapter 3, “Alternate

Configuration Modes”). When the highest-performance configuration is required, the

Platform Flash XL must be used with the FPGA in Slave SelectMAP mode. The Master

SelectMAP or Master BPI can be considered in cases where less configuration performance

is needed and the FPGA Fallback feature is needed.

In addition to high-performance configuration, Platform Flash XL provides a 128 Mb

(8M x 16 bits) nonvolatile single-chip flash memory configuration solution with a small

footprint (FT64) and advanced system-level capabilities. A standard NOR flash interface

(Figure 1-1) and support for common flash interface (CFI) queries provide

industry-standard access to the device memory space. Platform Flash XL’s 128 Mb capacity

can hold one or more FPGA bitstreams, with any unused memory available for

general-purpose data or embedded processor code storage. For bitstream requirements,

see U

G191, Virtex-5 FPGA Configuration User Guide or UG360, Virtex-6 FPGA Configuration

User Guide.

The Platform Flash XL signals and functions are described in Table 1-2. See Chapter 2,

“High-Speed Configuration” and Chapter 3, “Alternate Configuration Modes” for

recommended connections to the FPGA.

X-Ref Target - Figure 1-1

Figure 1-1: Platform Flash XL Logic Diagram

Table 1-2: Platform Flash XL Signal Descriptions

Signal Name Function Direction

A[22:0] Address inputs Inputs

DQ[15:0] Data input/outputs, command inputs I/O

Chip enable Input

Platform

Flash XL

READY_WAIT

A[22:0]

SSQ

DDQ

DQ[15:0]

UG438_C01_01_081309

14 www.xilinx.com Platform Flash XL Configuration & Storage Device

UG438 (v3.0) August 5, 2015

Chapter 1: Overview

— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —

For FPGA designs that require data storage, the Platform Flash XL has a multiple-bank

architecture—an array of 131 individually erasable blocks that are divided into sixteen

8 Mb banks. Fifteen main banks contain uniform blocks of 64 Kwords, and one parameter

bank contains seven main blocks of 64 Kwords, plus four parameter blocks of 16 Kwords

(the parameter blocks are located at the top of the memory address space in Platform Flash

XL). The device has a 23-bit address bus providing random read access to each 16-bit word.

See DS617

, Platform Flash XL High-Density Configuration and Storage Device for memory map

information and application programming instructions.

The device is in-system programmable with a 1.8V core (V

) power supply

(electronically erasable at the block level and programmable on a word-by-word basis). A

separate I/O (V

DDQ

) power supply enables I/O operation at 2.5V or 3.3V.

The ISE

iMPACT software supports indirect, in-system programming of

Platform Flash XL via the IEEE Standard Test Access Port and Boundary-Scan Architecture

(IEEE Std 1149.1) port (i.e., the JTAG port) on the FPGA (see Chapter 6, “Programming

Platform Flash XL”).

For FPGA configuration, the Platform Flash XL powers-on directly into synchronous read

mode. After latching a starting read address, the synchronous read mode enables the flash

to output its array data as a continuous stream of 16-bit words based on an internally

incrementing address counter. In each clock cycle, a 16-bit word is delivered. The Platform

Flash XL's interface can latch the starting address at the beginning of the FPGA's

SelectMAP or BPI mode configuration sequence. The Platform Flash XL's synchronous

read function is directly compatible with the FPGA's SelectMAP or BPI mode

configuration interface.

G Output enable Input

Write enable Input

Reset Input

Write protect Input

K Clock Input

Latch enable Input

READY_WAIT Ready wait I/O

Supply voltage –

DDQ

Supply voltage for input/output buffers –

Optional supply voltage for fast program and

erase

–

Ground –

SSQ

Ground input/output supply –

Table 1-2: Platform Flash XL Signal Descriptions (Cont’d)

Signal Name Function Direction

Platform Flash XL Configuration & Storage Device www.xilinx.com 15

UG438 (v3.0) August 5, 2015

— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —

Chapter 2

High-Speed Configuration

Slave SelectMAP Configuration Mode

Applications including PCI Express

systems require fast FPGA configuration. Platform

Flash XL provides the highest performance and power sequencing immunity in the Slave

SelectMAP mode. Platform Flash XL achieves maximum configuration performance when

a precise external clock source drives the FPGA Slave SelectMAP configuration mode up to

the maximum 50 MHz burst read frequency limit (CCLK) of the device.

This chapter describes the configuration of an FPGA from Platform Flash XL in Slave

SelectMAP configuration mode (M[2:0] = 110). The first section of this chapter describes

the required setup for Slave SelectMAP configuration and indirect in-system Platform

Flash XL programming (see Figure 2-1 and Figure 2-2). Next, the FPGA configuration flow

for this mode is demonstrated (see Figure 2-3). Refer to the SelectMAP Configuration

Interface section in UG191

, Virtex-5 FPGA Configuration User Guide or

UG360

, Virtex-6 FPGA Configuration User Guide, for additional information on the Slave

SelectMAP mode.

The Platform Flash XL has these system-level requirements for configuring an FPGA in the

FPGA's SelectMAP mode:

• An external clock source drives the synchronous bitstream transfer resulting in a

precise FPGA configuration time.

• On board pull-up or pull-down resistors set the configuration device control pins for

output read mode.

• On board pull-up or pull-down resistors set the configuration device burst read start

address.

• The FPGA does not support the Fallback feature in the Slave SelectMAP mode.

However, an external configuration manager (for example XAPP693

, A CPLD-Based

Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs) can be

implemented to achieve the equivalent fallback function.

See Figure 2-1, page 16 or Figure 2-2, page 18 for example Slave SelectMAP configuration

mode connections with the Virtex-5 FPGA or Virtex-6 FPGA, respectively. Refer to “Slave

SelectMAP Configuration from Platform Flash XL,” page 27 for details on the Slave

SelectMAP configuration sequence.

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