Kaby Lake U & Y平台设计指南：下一代超薄本与2合1设备
需积分: 16 71 浏览量
更新于2024-07-04
1
收藏 30.73MB PDF 举报
本设计指南是针对基于Kaby Lake处理器的Kaby Lake U和Y平台的主板实施建议，适用于下一代2合1设备和超薄笔记本电脑。发布于2016年11月，修订版2.1，由Intel公司提供。文档编号为CDI/IBP#564041，强调了Intel Confidential性质，意味着用户不得用于任何涉及Intel产品侵权或法律分析的活动。
Kaby Lake系列处理器通过其特性使得新型便携式设备性能得以提升，支持轻薄型设计，适合2合1设备和超极本的发展趋势。该指南详细涵盖了设计要点，包括但不限于：
1. **处理器架构与技术**：Kaby Lake采用了英特尔当时的先进技术，可能包括改进的微架构、更高效的能效比、以及针对低功耗和高性能计算的新功能，如Intel HD Graphics的增强，以支持多任务处理和图形密集型应用。
2. **主板接口与连接**：指南提供了关于主板接口、总线标准（如PCIe 3.0或Thunderbolt 3）和内存兼容性的指导，以确保最佳性能和稳定性。同时，它可能会涉及如何优化CPU与内存、硬盘和其他外设的通信。
3. **电源管理与散热**：随着性能的提升，散热设计和电源管理策略变得尤为重要。设计者需要遵循指南中的建议，以避免过热并确保长期稳定运行。
4. **功耗与电池续航**：Kaby Lake的低功耗特性对于延长电池续航至关重要，指南中会给出相应的电源管理和优化策略，以最大化设备的待机时间和使用时间。
5. **安全与合规性**：文档强调检查系统制造商或零售商，因为某些功能可能需要硬件激活或软件服务才能实现，同时也提醒用户注意潜在的设计缺陷或错误，如BIOS更新和固件安全。
6. **法律条款**：在使用这份设计指南时，用户同意授予英特尔非独家、无版税的专利许可，涵盖在此文档中披露的技术，但不包括任何知识产权的授予，且用户必须遵守相关法律条款，不得用于侵权行为。
这份设计指南对于Kaby Lake U和Y平台的硬件开发者和制造商来说，是一份重要的参考文档，帮助他们优化产品设计，充分利用处理器的优势，同时遵循英特尔的规范和最佳实践。
16 Intel Confidential Design Guide
2-7 KBL UMCP Dual-Stripline 8-Layer Type 3 PCB Stack-Up ..............................................20
2-8 KBL UMCP Layer Type 3 PCB Stack-Up .....................................................................21
2-9 KBL UMCP 10-Layer Type 4 PCB Stack-Up 2-x-2+ (L5, L6 is ½ oz.copper) ....................22
2-10 KBL UMCP 10-Layer Type 4 PCB Stack-Up 2-x-2+ (L5, L6 is 1 oz. copper) ....................22
2-11 KBL UMCP 10-Layer Type 4 PCB Stack-Up 1-x-1+......................................................23
2-12 KBL Y MCP 10-Layer Type 4 PCB Stack-Up - Option 1.................................................23
2-13 KBL Y MCP 10-Layer Type 4 PCB Stack-Up - Option 2.................................................24
2-14 Staggered versus Stacked Microvias ........................................................................33
2-15 Type 4 PCB PTH to Microvia Keep Out ......................................................................33
2-16 Backward Coupling Coefficient.................................................................................34
2-17 Forward Coupling Coefficient...................................................................................34
2-18 Single Ended Kb Diagram .......................................................................................35
2-19 Differential Kb Diagram..........................................................................................35
2-20 Common Glass Cloths Used in PCB Manufacture ........................................................36
2-21 Inhomogeneous Nature of PCB as Shown in this Cross-Section ....................................36
2-22 Effect of Skew on Differential and Common Mode Signals ...........................................37
2-23 Cross-Section of PCB Indicating Effect of PCB Fiber Weave..........................................37
2-24 An Example of Offset Routing..................................................................................38
2-25 An Example of Zig-Zag Routing ...............................................................................39
2-26 An Example of Slanted Routing ...............................................................................39
2-27 An Example of a PCB Cut Such That Its Edges are Rotated Relative to the Fiber Weave
Pattern ................................................................................................................40
2-28 Snapshot of PseudoSim..........................................................................................42
2-29 Snapshot of Electrical Channel Simulator (ECS) .........................................................43
2-30 Snapshot of freqMasterEx Toolbox ...........................................................................44
2-31 Snapshot of TlineCalc.............................................................................................45
3-1 Length Matching Example.......................................................................................48
3-2 Serpentining Example ............................................................................................48
3-3 Etch Located within a Pad Example ..........................................................................49
3-4 Example of Good Length Matching ...........................................................................49
3-5 Example of Poor Length Matching ............................................................................50
3-6 Tx-over-Tx, Rx-over-Rx, and Tx-over-Rx ..................................................................51
3-7 Dual-Stripline Orthogonal Routing Recommendation...................................................51
3-8 Dual-Stripline High Speed Signal Dual Layer Routing Recommendation.........................51
3-9 Recommended Routing Angle to Reduce Layer-to-Layer Crosstalk................................52
3-10 Via Pair Example ...................................................................................................52
3-11 Example - Via Placement 2 .....................................................................................53
3-12 Board Breakout Example - Via Placement 3...............................................................53
3-13 Differential Transitional Via Layout..........................................................................54
3-14 Acceptable Bends versus Tight Bends Example ..........................................................55
3-15 Maximum Bend Angle ............................................................................................55
3-16 Example Port Assignment for KBL UDocking Connector...............................................58
3-17 Recommended Differential Insertion Loss On Mated Docking Connector ........................59
3-18 Recommended Differential Return Loss On Mated Docking Connector ...........................59
3-19 Recommended Differential Crosstalk Limits On Mated Docking Connector......................60
4-1 KBL Y LPDDR3 x32 Memory Down Placement and Block Diagram .................................64
4-2 KBL Y LPDDR3 x32 Memory Down Strobe/Data/RCOMP Signal Topologies .....................65
4-3 KBL Y LPDDR3 x32 Memory Down CLK/CKE/CMD Signal Topologies..............................65
4-4 KBL Y LPDDR3 x32 Memory Down CTRL Signal Topologies ..........................................65
4-5 KBL Y LPDDR3 x32 Memory Down Placement and Block Diagram .................................69
4-6 KBL Y LPDDR3 x32 No VTT, No RTT for CMD/CTRL/CLK- Strobe/Data/RCOMP Signal
Topologies............................................................................................................70
4-7 KBL Y LPDDR3 x32 No VTT, No RTT for CMD/CTRL/CLK - CLK/CKE/CMD Signal Topologies .
70
4-8 KBL Y LPDDR3 x32 No VTT, No RTT for CMD/CTRL/CLK - CS/ODT Signal Topologies .......70
剩余785页未读，继续阅读
2017-12-27 上传
2023-05-30 上传
2023-07-28 上传
2023-10-12 上传
2023-05-15 上传
2019-04-22 上传
爱的si念
- 粉丝: 3544
- 资源: 54
我的内容管理
展开
最新资源
- 李兴华Java基础教程：从入门到精通
- U盘与硬盘启动安装教程：从菜鸟到专家
- C++面试宝典：动态内存管理与继承解析
- C++ STL源码深度解析：专家级剖析与关键技术
- C/C++调用DOS命令实战指南
- 神经网络补偿的多传感器航迹融合技术
- GIS中的大地坐标系与椭球体解析
- 海思Hi3515 H.264编解码处理器用户手册
- Oracle基础练习题与解答
- 谷歌地球3D建筑筛选新流程详解
- CFO与CIO携手：数据管理与企业增值的战略
- Eclipse IDE基础教程：从入门到精通
- Shell脚本专家宝典：全面学习与资源指南
- Tomcat安装指南：附带JDK配置步骤
- NA3003A电子水准仪数据格式解析与转换研究
- 自动化专业英语词汇精华：必备术语集锦
