2019年欧洲固体电路会议特辑：先进7nm FinFET V带隙参考等创新技术

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《JSSC-2019-7》是IEEE Journal of Solid-State Circuits (JSSC) 2019年7月刊的一期特辑，特别关注第48届欧洲固体电路会议(ESSCIRC)的相关研究。该期刊专注于固态电路的设计，特别是晶体管级集成电路(IC)的开发。在这一期中，论文经过严格的同行评审过程，遵循IEEE PSPB Operations Manual 的规定，采用单盲审稿方式，确保了学术质量。文章涵盖了多种创新和实用的电路设计和技术，如： 1. **A1-V Bandgap Reference in 7-nm FinFET** - 提供了一种具有可编程温度系数和在-45°C至125°C之间精度高达±0.2%的新型7纳米FinFET V带隙参考电路。这对于高性能、低功耗的微电子设备中的温度补偿至关重要。 2. **A 0.1-nW – 1 µW Energy-Efficient All-Dynamic Capacitance-to-Digital Converter** - 介绍了一个能效极高的全动态转换器，将电容信号转换为数字信号，对于能源管理的微型传感器和通信系统有重大影响。 3. **Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor** - 研究了一种针对旋转霍尔电流传感器的快速过流检测器，结合ping-pong和chopping技术，提高了测量的实时性和准确性。 4. **Robust BBPLL-Based 0.18-µm CMOS Resistive Sensor Interface** - 一篇关于基于宽带锁相环(BBPLL)的高抗漂移0.18微米CMOS电阻式传感器接口的研究，展示了在宽温范围(-40°C 至175°C)内的优异性能。 5. **15-nW per Sensor Interference-Immune Readout IC for Capacitive Touch Sensors** - 介绍了一种专为抗干扰设计的传感器读出集成电路，适用于触摸传感器应用，尤其是在对能耗敏感的移动设备中。此外，本期还包括了分析与设计的文章，反映了当前前沿电路技术和对低功耗、高性能、温度适应性强的系统需求的深入理解。这些研究不仅推动了集成电路技术的发展，也为电子工程领域提供了实用的解决方案和设计思路。通过阅读这一期的JSSC，读者可以了解到最新的固态电路创新，以及它们如何应用于日益复杂和多样化的电子产品中。

MOUSAVI et al.: 0.4–1.0 GHz, 47 MHop/s FH TXR FRONT END WITH 20 dB IN-BAND BLOCKER REJECTION 1919

the N-path-based correlators. The residual TX signal after the

SIC is orthogonal to the RX LO and, hence, gets reduced

by the correlator. Due to the ultra-fast hopping speed of the

transceiver, the rejection is limited, and a portion of this power

shows up in the receiver channel. The sinc ﬁlter response

caused by the fast hopping has its ﬁrst null at the hop rate

of 47 MHz. Therefore, there is still signiﬁcant TX energy in

the RX channel. The transmitted signal over one symbol can

be written as shown in (1), where P[t] is the rectangular pulse,

is the hop time, N is the total number of channels, f

is the

transmit frequency at the ith hop, and 

(i) is the necessary

phase at the ith hop at the transmitter to ensure continuity

between the frequency hops

x(t) =



i=1

P[t −(i − 1)T

]sin[2π f

t + 

(i)]. (1)

The signal at the receiver then is given by (2), where f

is the

receive frequency and 

(i) is the necessary phase at the ith

hop at the receiver to ensure continuity between the frequency

hops

y(t) =



i=1

P[t −(i −1)T

]sin[2π f

t +

(i)]e

j2π f

t+

(i)

(2)

The spectrum at the receiver can be estimated by perform-

ing the Fourier transform of (2), which can be written as

shown in the equation in the following. Here, we note that

the transmitter and receiver channels are distinct and that the

ﬁnal spectrum has a sinc shape that is proportional to the

hop-time T

. This means that even if RX and TX channels are

different, there is still going to be spill over from TX to RX.

The spacing between TX and RX frequencies alters the phase

and the sinc magnitudes of each of the summation terms that

fall in-band and changes the self-interference that shows up in

the RX band. As the hopping speed increases, T

decreases,

which widens the sinc function that causes more energy to

show up in the RX baseband. This problem is normally not

seen at lower hopping speeds, as the sinc main lobe is much

narrower. We have veriﬁed this phenomenon via numerical

simulations and also via measurements as discussed later.

Y ( f ) =

2 j



i=1

−j (2i−1)πT

( f −f

)

×[Sinc(T

( f − f

− f

)

×e

j ((2i−1)πT

( f

−f

)+

(i)+

(i)

−Sinc(T

( f − f

+ f

)

×e

−j ((2i−1)πT

( f

−f

)+

(i)+

(i)

Our measurement results for the transmit signal seen at the

RX channel for a ten-channel separation between the TX and

RX show a 27 dB suppression of the TX signal. For the 8 dBm

TX signal input at the antenna and 20 dB suppression by the

SIC, this results in a −40.4 dBm self-interference in the RX

channel, as shown in Fig. 2. The broadband TX noise signal

can be suppressed in the digital baseband using an axillary path

as in [10] and is not included in this prototype. In the case of

the PA, the primary limitation is that since the TX correlators

are before the PA, the PA needs to be able to pass the fast

hopping signal, i.e., it has to be sufﬁciently broadband. Not

surprisingly, broadband PAs are normally less power efﬁcient

than high-Q narrow-band PAs.

B. Receive Correlator

The receive correlator consists of two passive four-phase

mixers. N-path mixers use passive switches and a 25% duty

cycle clock generator (for four-phase). These are “digital-

like,” in which they do not have any memory and can

switch frequencies instantly. The only element that maintains

memory is the baseband ﬁlter capacitor. As long as the RF

and LO frequencies are synchronized, the memory element

effectively only sees signals close to dc. The mixer on the

left that is synchronized to the received signal de-spreads and

down-converts the desired signal to baseband. At the same

time, the mixer also spreads out any narrow-band blockers

that may exist in-band. The de-spread signal is then ﬁltered

out to remove any out of band interference. In our design,

the de-spreading/processing gain is 20 dB. The blocker is also

reduced by the same amount. The reason for the processing

gain is that the receiver only sees the blocker once every

100 times, effectively reducing its power by a 100 times

or 20 dB. The same thing happens when there are multiple

blockers in-band, i.e., the receiver spreads the blockers such

that the sum of the powers of the resulting spectrums that

show up in the receive channel is 20 dB down. Note that the

spreading and ﬁltering/averaging of the blocker occur in the

current domain, which means that large voltage swings due to

the interferer are avoided.

The resulting baseband signal is then up-converted to a

ﬁxed-frequency RF. As discussed previously, the reason for

this up-conversion is that the front end can be added to

any commercial off-the-shelf (COTS) transceiver, which also

allows us to exploit the excellent noise ﬁgure of COTS low

noise ampliﬁer (LNA).

C. Transmit Correlator

The transmit correlator down-converts the ﬁxed-frequency

transmit signal with the mixer to the right and up-converts

it back to RF using the fast-hopping LO signal. Similar

to the receive correlator, the double mixer structure makes

this correlator suitable for use with COTS transceivers. The

ﬁxed-frequency mixers in the receive and transmit correlators

may be removed for an integrated solution.

The hopped transmit signal is then ampliﬁed using a broad-

band linear PA. An example broadband PA that meets our

speciﬁcations is given in [11]. The PA is operated with 5 dB

backoff to insure linear operation. The 33 dBm PA output

power is fed to the antenna using an off-chip circulator.

This output power enables the transceiver to support a range

of 1.5 Km for the 3 GPP suburban channel model, assuming

that 30 dBm power is radiated from the antenna. The transmit

correlator is placed before the PA to relax its power handling

requirements. However, this means that a high-Q narrow-band

PA may not be used, as it will ring during channel hopping.

1920 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 7, JULY 2019

Fig. 3. DDS versus DO power consumption and maximum clock frequency

(see [13]–[24]).

D. Self-Interference Cancellation Circuit

Part of the large transmit signal at the PA output leaks into

the receiver side due to the ﬁnite isolation of the front-end

circulator. Assuming 25 dB-isolation [9], the self-interference

can be as large as 8 dBm at the input of the receive correlator

and limits its linearity. The SIC circuit (SIC canceller) is

therefore added to cancel a part of this signal. The circuit

is placed after the PA so that any signals due to the PA

nonlinearity are also canceled. It does not consume dc power

and does not degrade receiver noise performance. The design

is based on the same principles as those described in [12] but

differs in implementation.

The PA noise is also attenuated by the circulator and shows

up in the receive band. The total in-band noise is given by the

integration of the attenuated PA noise in a 0.6 MHz band,

which is very small in our design and does not limit the

performance. For designs where the PA noise is an issue,

an extra auxiliary path can be added to cancel the PA noise

in the baseband. Previous works have demonstrated 20 dB of

cancellation [10].

E. LO Signal Generator

A potential approach to generate the ultra-fast hopping sig-

nals is to use a direct digital synthesis (DDS). DDS circuits are

designed to generate any custom periodic signal and therein lie

its disadvantage. Here, our goal is to generate the LO signal

only. The LO signal can be either a sine wave or a square

wave (i.e., odd harmonics are not critical). In comparison to

our design, DDS circuits consume signiﬁcantly more power,

as shown in Fig. 3. This can be intuitively explained due to the

limited function required of the digital oscillator (DO), which

generates a sine wave only, while DDSs are able to generate

any type of periodic signal. In addition, due to its operational

mode, the digital-to-analog converter (DAC) resolution in our

signal generator can be of a lower resolution. The power

consumption of our prototype in mW/GHz is an order of

magnitude smaller than prior DDS designs.

In our design, the programmable LO signal is in the range

of f

clk

/4, i.e., the oversampling ratio is only around two.

We therefore require a reconstruction ﬁlter at the output of the

DAC that removes the other unwanted harmonics. The digital

Fig. 4. (a) Structure of the digital oscillator with an additive quantization

noise model. (b) DO output with continuous phase between frequency jumps.

oscillator is based on a design presented in [25]. The original

design was made to drive a bandpass sigma-delta DAC and

was designed for lower speeds. The improved version of the

design is shown in Fig. 4 (left). The new design halves the

number of multipliers and integrators, allowing it to operate

at higher speeds. The center frequency is set by setting the

value of r

in Fig. 9 (left).

The transfer function from r

to the output x(n) for the

DO in Fig. 4 is given by (3). Fig. 4 also includes a model

for the quantization error in the DO and will be discussed

later. The roots of the resulting characteristic equation give us

the oscillating frequency. In particular, the input variable r

limited from −2 to 2 to provide real values, and therefore,

the poles can be written, as shown in (4). As a result,

the precise output frequency can be simpliﬁed to (5)

x(n − 2) +r

x(n − 1) + x(n) = 0(3)

1,2

−r

± j



1 −

= e

±jcos

−1

(−

)

(4)

out

clk

cos

−1

(−

)

2π

. (5)

When r

= 0, f

out

= f

clk

cos

−1

(0)/2π = f

clk

/4. The

output frequency range can be varied from near 0 to f

clk

/2.

1) Frequency Error From Computational Accuracy: The

DO output frequency is determined by the value of r

and

the input clock frequency. The frequency error is determined

by the digital computation accuracy. The amplitude of the DO

output is solely determined by the initial conditions of the

two registers [25]. Next, we discuss the digital computational

accuracy needed versus the frequency error of the digital

oscillator.

Fig. 4 (right) shows the ideal output when ﬂoating-point

computation is used. Note that the phase is continuous between

frequency hops. Fixed-point computation is more suitable for

low-power design, but ﬁnite computation resolution is likely to

degrade the frequency accuracy. Our design uses 100 channels.

Fig. 5 shows the frequency error in Hz for all the 100 channels

versus the computation accuracy for a tuning range from

clk

/6to f

clk

/3. The computational accuracy is varied between

12 and 20 bits. For 16 bit computational accuracy, the maxi-

mum one-sided frequency error is 325 Hz, which corresponds

to 0.84 ppm. Most wireless systems allow the crystal oscillator

to have a maximum deviation of 10–20 ppm. We wanted to

ensure that the DO did not contribute signiﬁcantly to this. The

computational accuracy is a compromise between frequency

MOUSAVI et al.: 0.4–1.0 GHz, 47 MHop/s FH TXR FRONT END WITH 20 dB IN-BAND BLOCKER REJECTION 1921

Fig. 5. Frequency deviation from ideal (frequency error) for all 100 channels

versus computational accuracy.

Fig. 6. Analytical model and numerical simulation for the DO phase noise.

error and power. The relationship between the frequency

output and the clock frequency given in (5) is nonlinear, and

therefore, for simplifying the design of the reconstruction ﬁlter

and for the modeling of the quantization noise, we limit our

input to lie between −1 and 1. All 100 channels lie within

this input range. We maintain the same number of computation

bits throughout the digital oscillator, i.e., the number of bits at

the output of multiplier is the same as at the input. Therefore,

choosing an r

value that is bounded by +1and−1 allows

us to simplify the design.

2) Phase Noise From Computational and DAC Accuracy:

In a transceiver, the phase noise of the LO has signiﬁcant

impact on the error vector magnitude (EVM) and on jammer

performance due to reciprocal mixing. The total phase noise

will include the contributions from: 1) the input clock; 2) the

digital oscillator; and 3) the LO DAC and injection locked

oscillator (ILO) and duty cycle generators for the correlators.

In this paper, we primarily focus on the contributions of the

digital oscillator and DAC, as other contributors are well

understood.

The DO model with quantization noise was shown in

Fig. 4 (left), where the input coefﬁcient to the DO, r

,sets

the oscillation frequency. Therefore, it stands to reason that

the quantization noise due to ﬁnite computation accuracy will

cause perturbations in the oscillation frequency, i.e., phase

noise. The only contributor to quantization noise is the digital

multiplier. In general, if two operations of w bits are mul-

tiplied, then the resultant can have a maximum of 2w bits.

However, in our system, the output is also limited to w bits,

as r

is limited by ±1, which bounds the quantization noise.

The quantization noise distribution for a multiplier where

one of the inputs is a constant is the same as the quan-

tization noise from a regular quantizer (i.e., ADC). Thus,

we can simplify our analysis by assuming that the quantization

noise can be modeled as an additive white noise [26]. Using

phase noise analysis methods similar to continuous-time LC

oscillators [27], we developed an analytical model for the

phase noise contribution of the computational accuracy of

digital oscillators. We used this analytical model to derive the

phase noise at 100 KHz and 1 MHz offsets for 8–16 bits of

accuracy. These are shown as diamonds in Fig. 6. In Fig. 6,

we plot the phase noise contribution of the DO separately by

building a bit-accurate model of the DO in MATLAB (lines).

For this simulation, we operate the DO with w bit resolution.

The output is then down-converted to baseband using an ideal

LO, and then, we perform an fast Fourier transform (FFT) on

the low-pass ﬁltered signal. We performed these simulations

for multiple resolutions between 8 and 16 bits. There is

good matching between the analytical model and numerical

simulations validating our white noise assumption. Thus, the

16 bit accuracy required from a frequency accuracy perspec-

tive results in a DO-only phase noise assuming an ideal

input source as −163 dBc/Hz at a 1 MHz offset. This is

much lower than the phase noise at the DO output from the

input source assuming an inﬁnite accuracy of −144 dBc/Hz

at a 1 MHz offset (discussed in Section IV). Thus, 16 bit

accuracy was considered to be sufﬁcient from both a frequency

accuracy and phase noise perspective. The 16 bit ﬁxed-point

digital oscillator was implemented in Verilog and synthesized

using a custom standard cell library in Taiwan Semiconductor

Manufacturing Company (TSMC’s) 65 nm technology.

The DO generates a binary sample-and-hold sinusoidal

signal with W bit resolution. The DO output is then converted

to the analog domain by a DAC. Because our goal is to hop

rapidly between frequencies, we have to use a memoryless

DAC, i.e., not a sigma–delta. The output from the M bit DAC

is then ﬁltered by an ILO with very high Q to remove the

unwanted harmonics. Prior work has shown that ILOs can act

as high-Q bandpass ﬁlters that can jump frequencies almost

instantly [4]. The fast-hopping nature of the DO, the DAC,

and the ILO enables the LO frequency to change almost

instantaneously. The settling time is primarily limited by the

digital circuits that provide the control signals.

III. C

IRCUIT DESIGN

Next, we provide the circuit details for the above-discussed

system blocks. In particular, we provide circuit details and

simulations to validate our design selections for the correlators,

the self-interference cancellation circuit, and the LO.

A. Transmit and Receive Correlators

The correlators are implemented as a set of four-phase

passive mixers with 25% duty cycle clocks, which is shown

in Fig. 7(a). The correlator design is essentially identical to

an N-path structure except that the input and output mixers

are operated at different frequencies. In an N-Path ﬁlter, both

1922 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 7, JULY 2019

Fig. 7. Circuit details for (a) transmit and receive correlators and

(b) self-interference cancellation circuit.

mixers are operated at the same frequency, and usually, one

is removed from the design for improved noise performance.

Here, we maintain the dual-mixer format for ﬂexibly and for

improved out-of-band performance [5]. For the transmitter,

the input mixers are connected to a ﬁxed-frequency LO, and

the other one is driven by an ultra-fast FH LO. The input

data are down-converted to baseband from a ﬁxed RF center

frequency and up-converted back to RF using the fast-hopping

LO signal. The same circuit is used for the receiver with

opposite directions. When synchronized, the receive correlator

down-converts the received hopping signal on the baseband

capacitors. The received signal is then up-converted to a ﬁxed

frequency and further processed by a COTS receiver. The

switches are implemented using 1 V RF nMOS devices,

and they have 3  series resistance when they are

ON.

The baseband capacitors are implemented using only MIM

capacitors so that the linearity is only limited by the nMOS

switches. The 25% duty cycle clocks are generated using a

divide-by-two ﬂip-ﬂop loop and standard logic operations [5].

The correlator is an RF bandpass ﬁlter that changes the

center frequency according to the LO signal. Hence, if two

tones exist in-band, they will generate an third order inter-

modulation product (IM3) products that may fall in-channel.

The low-frequency LTI model for N-path ﬁlters was presented

and validated in [28]. We use this same model plus insight

from [29] to develop an analytical model to evaluate the ratio

between in-band third order intercept point (IIP3) and out-

of-band IIP3 for our design. The simpliﬁed circuit model

of a top-plate switch circuit is shown in Fig. 8 (top). The

large jammer causes V

of the switch to vary [29]. As the

frequency moves away from the channel center, the capacitor

becomes more of a short reducing the signal amplitude of the

jammers.

In our system, our channel hops but the jammers are

assumed to be stationary. However, for a simpler analysis,

we assume that our channel is stationary and the jammers

hop. In our case, we have a total of 100 channels but only

certain combinations of two tones fall in-band. The cases

for which the IM3 products falls in the channel are shown

in Fig. 8. The ﬁrst row shows the channel number in which

the ﬁrst tone exists. The second row shows the second tone

channel that results in an IM3 product, which falls in-channel.

Fig. 8. Out-of-band IM3 product reduction due to baseband ﬁlter response.

Fig. 9. (a) DO structure. (b) Current-mode 8 bit DAC. (c) Buffer included

for testing purposes only.

The suppression of the IM3 product due to the baseband

ﬁltering is shown in the third row. The IIP3 improvement

compared with the in-band IIP3 is the average value of all

the suppression values for the other 99 channels. This results

in a 20.1 dB IIP3 improvement for output-of-band IIP3 in

comparison with in-band IIP3. The calculations provided here

are in reasonable agreement with the previously published

results [29].

B. Self-Interference Canceller Circuit

Due to high PA power, the self-interference canceller circuit

needs to be very linear suggesting a passive structure. The cir-

cuit should also have minimal impact on the noise ﬁgure (NF)

of the receiver. As shown in Fig. 7(b), the circuit is imple-

mented using resistors, capacitors, and switches and is similar

to the design in [12]. The design in [12] uses an R-2R and

C-2C ladder networks. We use binary resister and capacitor

ratios. Both designs start with the NF consideration ﬁrst. It can

be shown that a 200  resistor only degrades the NF by 0.5 dB

when the receiver NF is 1 dB. This means that the smallest

combination of the resistors in the circuit needs to be larger

than 200 s. The capacitors are then sized accordingly. The

switches are located on the receive side where cancellation

occurs, as they do not see large voltage swings. The circuit

does not consume any DC power. Dynamic power is small

due to slow reconﬁguration speed which, at maximum, only

operates at the hop rate.

C. Ultra-Fast Hopping Signal Generator

The overall circuit design for LO generation is shown

in Fig. 9, and the DO architecture has been discussed ear-

lier. Next, we consider the impact of DAC resolution on

MOUSAVI et al.: 0.4–1.0 GHz, 47 MHop/s FH TXR FRONT END WITH 20 dB IN-BAND BLOCKER REJECTION 1923

Fig. 10. (a) Chip microphotograph. (b) Received 64 QAM signal.

the overall LO phase noise. The current-mode DAC puts

out a ﬁnite resolution sample-and-hold analog value. Ideally,

the ﬁnite quantization contributes broadband additive noise but

does not directly cause phase noise. However, the broadband

quantization at the DAC output can get converted to phase

noise due to ﬁnite rise and fall times and due to the AM-to-

PM conversion of the buffer or ILO that follows the DAC.

To evaluate this contribution, we used the same test setup as

the DO quantization but with varying DAC resolution. This

simulation was done in Cadence using PNOISE where an

equivalently shaped Gaussian noise model substitute was used

for quantization noise to achieve convergence. The authors are

aware that the probability density function of the two noise

sources (quantization versus Gaussian) are different but the

expected values and frequencies were appropriately adjusted

and we expect that this should provide a good approximation.

If we assume that the input clock is ideal and that the digital

part of the DO generates no phase noise, then the phase noise

contribution due to the AM-to-PM conversion of the 8 bit DAC

alone at a 1 MHz offset is −136 dBc/Hz. Actual phase noise

measurements will be a function of the phase noise from the

source, the computational accuracy, and the contributions from

the DAC AM-to-PM. The DAC system is being redesigned

with a larger number of bits.

IV. M

EASUREMENT RESULTS

The design was fabricated in the TSMC’s 65 nm RF-GP

CMOS technology. The active area is 3.1 mm

. The micropho-

tograph of the fabricated chip is shown in Fig. 10(a). Next,

we present measurement results for the various components

of the system, i.e., the correlators, the DO, and the DAC.

This set of measurements is followed by more system-level

measurements, including TX to RX intended signal, TX to

RX self-interference, and narrow-band jammer rejection.

A. Component-Level Measurements

First, we provide measurements for the fast-hopping critical

components, including the correlator and the LO path.

1) Correlator Measurements: Fig. 11(a) shows a spec-

trogram of the transmit correlator while hopping between

two frequencies centered at 1 GHz. For this and the next

measurement, the LO signal that drives the output mixers

of the transmit correlator is hopped, and the output of the

correlator is measured using a 20 GSa/s R&S oscilloscope.

Fig. 11. (a) Frequency-hopping spectrogram used to measure the transient

response of the correlator. (b) Measured TX correlator transient response. Only

two hopping frequencies are shown here to ease transient response behavior.

Fig. 12. Transmit correlator output spectrum for random FH LO.

Due to IF bandwidth limitations of our spectrum analyzer,

transient response measurements are performed by using the

time-domain sampled values of the output using a digital

oscilloscope. The data are then taken to MATLAB, interpo-

lated and ﬁltered, and a spectrogram performed on the output.

As can be seen, we clearly see the hopping pattern but it is

difﬁcult to measure the exact transient response time using the

spectrogram.

To better evaluate the transient response, we estimate the

instantaneous frequency by looking at the zero crossings of the

time-domain signal. Fig. 11(b) shows the transient response

of the transmit correlator to an abrupt frequency change in

the LO signal. The time resolution using the zero-crossings

method is limited to one half period, i.e., 0.5 ns when the

output is centered at 1 GHz. The blue line shows the measured

signal. The orange line shows the average of 200 data points.

The perturbations in the measurement are due to the ﬁnite

oversampling (≈2) and the practical limitations of the inter-

polation. The measured settling time is 0.5 ns, which means

that the correlator output frequency settles in less than 0.5 ns.

This shows that the correlator is able to hop nearly instantly

and the settling time is only limited to the fast-hopping LO

that drives the correlator.

Fig. 12 shows the transmit output spectrum on a spectrum

analyzer centered at 1 GHz. For this measurement, a dc input

value was provided at the baseband for a ﬁxed LO. The LO

was then hopped randomly across all 100 channels to occupy

a bandwidth of 60 MHz. Due to the divide-by-two circuit in

the N-path LO generator, the external LO input was centered

at 2 GHz and was hopped randomly to cover 120 MHz.

In Fig. 12, we see the spreading of the single sinusoidal spread

across the 100 channels providing 20 dB of processing gain.

2) DO and DAC Measurements: Next, we evaluate the

combined DO and DAC transient performance. Fig. 13(a)

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