2010年TMS320C64x/C64x+ DSP CPU新指令集详解

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本文档是关于TI公司TMS320C64x/C64x+ Digital Signal Processor (DSP) CPU和指令集的参考指南，发布于2010年7月。它提供了对C64x/C64x+ DSP系列的详细介绍，包括其特性和选项、架构以及核心处理器的工作原理。 1. **TMS320 DSP家族概述** 该部分介绍了TMS320 DSP家族的整体架构，着重提到了C6000系列，这暗示了C64x/C64x+是该系列中的一个高级成员，可能拥有更强大的性能和特性。 2. **TMS320C64x DSP的特性和选项** 这部分详细列出了C64x DSP特有的功能和可选配置，这些可能包括优化的数据处理能力、并行计算单元或特定的硬件加速功能，以适应多样化的应用需求。 3. **CPU架构** C64x/C64x+ DSP的核心组成部分包括中央处理器（CPU），内建内存，以及内存和外设接口。CPU设计可能涉及到多级流水线结构、多个通用寄存器文件和功能单元，确保高效的数据处理。 4. **数据路径和控制** - **数据通路**：文档涵盖了不同类型的通路，如一般目的寄存器文件、功能单元间的连接路径，以及与内存、加载/存储操作和数据地址相关的路径。 - **Galois Field**：C64x/C64x+ DSP可能利用Galois域进行特殊数学运算，这部分提到了特殊时序考虑，强调了在使用这类运算时需要注意的事项。 - **控制寄存器**：文档详述了访问控制寄存器的方式，如地址映射、访问时序和中断清除机制等，这些都是理解和编程CPU的关键要素。 5. **文档详细程度** 由于这是一份详细的参考指南，它不仅提供技术规格，还涉及了如何通过控制寄存器进行高级操作，以及处理异常情况如中断的管理，这对于开发人员来说是非常实用的信息。阅读这份文档能帮助开发者深入了解TMS320C64x/C64x+ DSP的硬件特性、指令集和工作原理，从而在实际项目中更有效地利用这些处理器进行信号处理和数字逻辑设计。对于从事嵌入式系统或DSP应用的工程师来说，这份文档是不可或缺的技术参考资料。

Related Documentation From Texas Instruments

www.ti.com

architecture in the C64x+ DSP is organized in a two-level hierarchy consisting of a dedicated

program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to

the these first level caches can complete without CPU pipeline stalls. If the data requested by the

CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external

memory.

SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital

signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access

(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth

management, and the memory and cache.

SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the

Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The

objective of this document is to indicate differences between the two cores. Functionality in the

devices that is identical is not included.

SPRU186 — TMS320C6000 Assembly Language Tools User's Guide. Describes the assembly

language tools (assembler, linker, and other tools used to develop assembly language code),

assembler directives, macros, common object file format, and symbolic debugging directives for the

TMS320C6000 platform of devices (including the C64x+ and C67x+ generations).

SPRU187 — TMS320C6000 Optimizing Compiler User's Guide. Describes the TMS320C6000 C

compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code and

produces assembly language source code for the TMS320C6000 platform of devices (including the

C64x+ and C67x+ generations). The assembly optimizer helps you optimize your assembly code.

SPRU198 — TMS320C6000 Programmer's Guide. Reference for programming the TMS320C6000

digital signal processors (DSPs). Before you use this manual, you should install your code

generation and debugging tools. Includes a brief description of the C6000 DSP architecture and

code development flow, includes C code examples and discusses optimization methods for the C

code, describes the structure of assembly code and includes examples and discusses optimizations

for the assembly code, and describes programming considerations for the C64x DSP.

TMS320C6000, TMS320, TMS320C62x, TMS320C64x, C6000, TMS320C67x, C62x, C64x, VelociTI, XDS510, XDS560, TMS320C2000,

TMS320C5000 are trademarks of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

Read This First SPRU732J–July 2010

TMS320C64x DSP Features and Options

www.ti.com

1.3 TMS320C64x DSP Features and Options

The C6000 devices execute up to eight 32-bit instructions per cycle. The C64x CPU consists of 64

general-purpose 32-bit registers and eight functional units. These eight functional units contain:

• Two multipliers

• Six ALUs

The C6000 generation has a complete set of optimized development tools, including an efficient

C compiler, an assembly optimizer for simplified assembly-language programming and scheduling, and a

Windows

operating system-based debugger interface for visibility into source code execution

characteristics. A hardware emulation board, compatible with the TI XDS510™ and XDS560™ emulator

interface, is also available. This tool complies with IEEE Standard 1149.1-1990, IEEE Standard Test

Access Port and Boundary-Scan Architecture.

Features of the C6000 devices include:

• Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units

– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs

– Allows designers to develop highly effective RISC-like code for fast development time

• Instruction packing

– Gives code size equivalence for eight instructions executed serially or in parallel

– Reduces code size, program fetches, and power consumption

• Conditional execution of most instructions

– Reduces costly branching

– Increases parallelism for higher sustained performance

• Efficient code execution on independent functional units

– Industry's most efficient C compiler on DSP benchmark suite

– Industry's first assembly optimizer for fast development and improved parallelization

• 8/16/32-bit data support, providing efficient memory support for a variety of applications

• 40-bit arithmetic options add extra precision for vocoders and other computationally intensive

applications

• Saturation and normalization provide support for key arithmetic operations

• Field manipulation and instruction extract, set, clear, and bit counting support common operation found

in control and data manipulation applications.

The C64x and C64x+ devices include these additional features:

• Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.

• Quad 8-bit and dual 16-bit instruction set extensions with data flow support

• Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses

• Special communication-specific instructions have been added to address common operations in

error-correcting codes.

• Bit count and rotate hardware extends support for bit-level algorithms.

In addition to the features of the C64x device, the C64x+ devices include these additional features:

• Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce

code size.

• Protected mode operation: A two-level system of privileged program execution to support higher

capability operating systems and system features such as memory protection.

• Exceptions support for error detection and program redirection to provide robust code execution

• Hardware support for modulo loop operation to reduce code size

• Each multiplier can perform 32 × 32 bit multiplies

• Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts

per clock cycle

Introduction SPRU732J–July 2010

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