TDA998x HDMI传输器详细参考手册：寄存器配置与功能特性

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TDA998x系列是一款通用的RCB转HDMI芯片，主要针对高清视频信号处理和音频输出设计。它集成了多种功能，包括HDMI 1.2标准兼容的视频传输、高达150MHz像素速率的3×8-bit RGB或YCBCR视频流支持、最多4路I2S音频总线接口，最高可支持192kHz的采样率。这款芯片的特点在于其灵活的性能和广泛的输入兼容性。作为一款高清视频解码和格式转换器，TDA9983B具备一个可编程的上采样模块，能够将标清信号（如720p/1080i）提升至高清分辨率输出。内部还包含一个帧内场间插补器，以提高图像质量。为了适应广泛的应用场景，TDA9983B集成了全程序化的输入格式化器和色彩空间转换模块，可以处理多种视频格式，包括YCBCR 4:4:4（最大支持3×8-bit）、YCBCR 4:2:2（半平面和符合ITU-R 656标准，最大支持2×12-bit），以及类似ITU-R 656格式，支持双边缘采样，确保数据在上升和下降沿精确传输。设备的控制方式采用I2C接口，这是一种低速串行通信协议，方便与其他微控制器或外设进行通信，简化了系统设计。此外，TDA9983B还具备CMOS和LV-TTL兼容的视频输入接口，以及用于水平同步、垂直同步和数据使能（DE）信号的VREF、HREF和FREF输入选项，这些特性使其能够在不同的电子系统中灵活集成。 TDA998x系列芯片凭借其丰富的功能、高度的灵活性和广泛的输入格式支持，成为构建高质量多媒体解决方案的理想选择，适用于各种消费电子设备和视听系统中，对视频信号的处理和输出有高要求的应用场合。通过深入理解和利用这些特性，开发人员能够优化系统性能，提供卓越的用户体验。

Product data sheet Rev. 01 — 20 May 2008 16 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

Table 12. YC

4:2:2 semi-planar external synchronization mappings

4:2:2 semi-planar external synchronization single edge.

Video port A Video port B Video port C Control

Pin YC

4:2:2

semi-planar

Pin YC

4:2:2

semi-planar

Pin YC

4:2:2

semi-planar

Pin YC

4:2:2

VPA[0] Y

[0] Y

[0] VPB[0] Y

[4] Y

[4] VPC[0] C

[4] C

[4] HSYNC/HREF used

VPA[1] Y

[1] Y

[1] VPB[1] Y

[5] Y

[5] VPC[1] C

[5] C

[5] VSYNC/VREF used

VPA[2] Y

[2] Y

[2] VPB[2] Y

[6] Y

[6] VPC[2] C

[6] C

[6] DE/FREF used

VPA[3] Y

[3] Y

[3] VPB[3] Y

[7] Y

[7] VPC[3] C

[7] C

[7]

VPA[4] C

[0] C

[0] VPB[4] Y

[8] Y

[8] VPC[4] C

[8] C

[8]

VPA[5] C

[1] C

[1] VPB[5] Y

[9] Y

[9] VPC[5] C

[9] C

[9]

VPA[6] C

[2] C

[2] VPB[6] Y

[10] Y

[10] VPC[6] C

[10] C

[10]

VPA[7] C

[3] C

[3] VPB[7] Y

[11] Y

[11] VPC[7] C

[11] C

[11]

Fig 9. Pixel encoding YC

4 : 2 : 2 semi-planar external synchronization (rising edge) input

001aag386

Y5 ...Y4Y3Y2Y1Y0

HSYNC/HREF

VSYNC/VREF

DE/FREF

4 ...C

CONTROL

INPUTS

VPB[7:0]; VPA[3:0]

VCLK

VPC[7:0]; VPA[7:4]

Product data sheet Rev. 01 — 20 May 2008 18 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

8.3 Synchronization

The TDA9983B can be synchronized with Hsync/Vsync external inputs or with extraction

of the sync information from embedded sync (SAV/EAV) codes inside the video stream.

8.3.1 Timing extraction generator

This block can extract the synchronization signals Href, Vref and Fref from Start Active

Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data

stream. Synchronization signals can be embedded in RGB, YC

4 : 4 : 4, YC

4:2:2 semi-planar (up to 2 × 12-bit), YC

4:2:2 ITU656 and ITU656-like (up to

1 × 12-bit).

8.3.2 Data enable generator

The TDA9983B contains a Data Enable (DE) generator; this can generate an internal DE

signal for a system which does not provide one.

8.4 Input and output video format

Due to the ﬂexible video input formatter, the TDA9983B can accept a large range of input

formats. This ﬂexibility allows the TDA9983B to be compatible with the maximum possible

number of MPEG decoders. Moreover, these input formats may be changed in many ways

(color space converter, upsampler, downsampler and scaler) to be transmitted across the

HDMI link. Table 14 gives the possible inputs and outputs.

8.5 Upsampler

The incoming YC

4 : 2 : 2 (2 × 12-bit) data stream format could be upsampled into a

12-bit YC

4 : 4 : 4 (3 × 12-bit) data stream by repeating or linearly interpolating the

chrominance pixels.

Table 14. Use of color space converter, upsampler, downsampler and scaler

Input Scaler Output

Color space Format Channels Color space Format Channels

RGB 4:4:4 3× 8-bit no scaling RGB 4:4:4 3× 8-bit

no scaling YC

4:2:2 2× 12-bit

no scaling YC

4:4:4 3× 8-bit

4:4:4 3× 8-bit no scaling RGB 4:4:4 3× 8-bit

no scaling YC

4:2:2 2× 12-bit

no scaling YC

4:4:4 3× 8-bit

4 : 2 : 2 up to 1 × 12-bit scalable YC

4:2:2 2× 12-bit

scalable YC

4:4:4 3× 8-bit

scalable RGB 4:4:4 3× 8-bit

up to 2 × 12-bit scalable YC

4:2:2 2× 12-bit

scalable YC

4:4:4 3× 8-bit

scalable RGB 4:4:4 3× 8-bit

Product data sheet Rev. 01 — 20 May 2008 19 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

8.6 Color space converter

The color space converter is used to convert input video data from one type to another

color space (RGB to YC

and YC

to RGB). This block can be bypassed and each

coefﬁcient is programmable via the I

C-bus register.

8.7 Downsampler

This block works only with YC

input format; these ﬁlters downsample the C

and C

signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the

pipeline delay of the ﬁlters, to put the Y channel in phase with the C

-C

channels.

8.8 Audio input format

The TDA9983B is compatible with HDMI 1.2a (DVD support). The TDA9983B can carry

audio in I

S-bus format (one stereo up to four stereo channels) or in S/PDIF format.

S/PDIF or I

S-bus format can be selected via the I

C-bus. Only one audio format can be

used at a time: either S/PDIF or I

S-bus. Table 15 shows the audio port allocation.

8.9 S/PDIF

The audio port AP6 is used for the S/PDIF feature. In this format the TDA9983B supports

2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream up to

8 multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9983B is able to

recover the original clock from the S/PDIF signal (no need for an external clock). In

addition it can also use an external clock (MCLK) to decode the S/PDIF signal.

8.10 I

S-bus

The TDA9983B supports the NXP I

S-bus format. There are four I

S-bus stereo input

channels (AP1 to AP4), which enable 8 uncompressed audio channels to be carried. The

S-bus input interface receives an I

S-bus signal including serial data, word select and

Y\G

G\Y

R\C

B\C

Oin

G\Y

Oin

R\C

Oin

B\C







Oout

Y\G

Oout

Table 15. Audio port conﬁguration

All audio ports are LV-TTL compatible.

Audio port I

S-bus and S/PDIF input conﬁguration

AP0 WS (word select)

AP1 I

S-bus audio port 0

AP2 I

S-bus audio port 1

AP3 I

S-bus audio port 2

AP4 I

S-bus audio port 3

AP5 MCLK (master clock for S/PDIF)

AP6 S/PDIF input

AP7 AUX (internal test)

ACLK SCK (I

S-bus clock)

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