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Section Number Title Page
15.5.2 Port Data Control Register 1 (AUDMUX_PDCR1)..................................................................................736
15.5.3 Port Timing Control Register 2 (AUDMUX_PTCR2)..............................................................................737
15.5.4 Port Data Control Register 2 (AUDMUX_PDCR2)..................................................................................739
15.5.5 Port Timing Control Register 3 (AUDMUX_PTCR3)..............................................................................740
15.5.6 Port Data Control Register 3 (AUDMUX_PDCR3)..................................................................................742
15.5.7 Port Timing Control Register n (AUDMUX_PTCRn)..............................................................................743
15.5.8 Port Data Control Register 4 (AUDMUX_PDCR4)..................................................................................745
15.5.9 Port Data Control Register 5 (AUDMUX_PDCR5)..................................................................................747
15.5.10 Port Data Control Register 6 (AUDMUX_PDCR6)..................................................................................748
15.5.11 Port Data Control Register 7 (AUDMUX_PDCR7)..................................................................................749
Chapter 16
40-BIT Correcting ECC Accelerator (BCH)
16.1 BCH Overview..............................................................................................................................................................751
16.2 Operation.......................................................................................................................................................................753
16.2.1 BCH Limitations and Assumptions...........................................................................................................754
16.2.2 Flash Page Layout......................................................................................................................................755
16.2.3 Determining the ECC layout for a device..................................................................................................757
16.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata, Assuming
GF(213)..................................................................................................................................757
16.2.3.2 4K+128 flash, 10 bytes metadata, 1024 byte data blocks, separate metadata, assuming
GF(213) for data and GF(214) for metadata..........................................................................758
16.2.4 Data Buffers in System Memory...............................................................................................................758
16.3 Memory to Memory (Loopback) Operation.................................................................................................................761
16.4 Programming the BCH/GPMI Interfaces......................................................................................................................762
16.4.1 BCH Encoding for NAND Writes.............................................................................................................763
16.4.1.1 DMA Structure Code Example..............................................................................................765
16.4.1.2 Using the BCH Encoder.........................................................................................................770
16.4.2 BCH Decoding for NAND Reads..............................................................................................................771
16.4.2.1 DMA Structure Code Example..............................................................................................775
16.4.2.2 Using the Decoder..................................................................................................................778
i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012
Freescale Semiconductor, Inc. 17
Preliminary - Subject to Change Without Notice
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