Marvell 88E1518千兆以太网PHY芯片手册

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本资源是一份关于Marvell生产的88E1510/88E1518/88E1512/88E1514系列集成10/100/1000Mbps Energy Efficient Ethernet（高效能以太网）收发器的数据手册。这份文档的标题表明了它提供了针对这些特定芯片的详细规格、功能和技术信息，对于需要设计或优化高速以太网通信系统的工程师和技术人员来说非常关键。手册的主要内容涵盖了以下几个重要知识点： 1. **产品概述**： - 这是一款集成了多种速率的以太网PHY芯片，支持10/100/1000Mbps的传输速度，适用于对数据传输效率和能效有高要求的应用场景。 - "MovingForwardFaster"强调了该芯片在提升网络性能方面的特性，可能涉及低功耗技术、高性能数据处理和信号处理能力。 2. **文档分类与版权信息**： - 文档为公开性质，日期为2018年2月23日，且必须经过Marvell的明确许可才能复制或传播。 - 提醒用户注意文档中的警告和注意事项，如可能对硬件或软件造成的损坏，以及数据丢失的风险。 3. **技术规范与功能**： - 数据手册详细列出了芯片的电气特性、物理接口规范、封装选项、以及可能的电气参数，如接收灵敏度、发送功率等，这对于确保兼容性和系统设计至关重要。 - "EnergyEfficientEthernet"表明芯片在设计上注重节能，可能包括低功耗模式、自动协商和节能特性等。 4. **无责任声明**： - Marvell明确表示不对其文档中的信息提供任何形式的担保，包括但不限于产品质量保证或特定用途的适用性，也警告用户不要依赖文档的准确性或完整性。 5. **获取更多信息**： - 提供了Marvell公司的网站链接，用户可以通过这个渠道获取更新的技术支持、产品更新和其他相关信息。这份88E1510/88E1518/88E1512/88E1514系列千兆以太网PHY芯片的数据手册是网络设备设计师和系统集成者不可或缺的参考资料，可以帮助他们了解如何有效地利用这些芯片构建高效能、低功耗的以太网通信系统。

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 16 Document Classification: Public February 23, 2018

Figure 34: MDC/MDIO Timing ........................................................................................................................138

Figure 35: ........................................................................................................................................................139

Figure 36: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing ........................................................140

Figure 37: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................141

Figure 38: 10/100/1000BASE-T to SGMII Latency Timing ..............................................................................142

Figure 39: SGMII to 10/100/1000BASE-T Latency Timing ..............................................................................142

5 Package Mechanical Dimensions .................................................................................................143

Figure 40: 88E1510/88E1518 48-pin QFN Package Mechanical Drawings ....................................................143

Figure 41: 88E1512/88E1514 56-pin QFN Package Mechanical Drawings ....................................................145

6 Part Order Numbering/Package Marking......................................................................................147

Figure 42: Sample Part Number ......................................................................................................................147

Figure 43: 88E1510 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................149

Figure 44: 88E1518 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 45: 88E1512 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 46: 88E1514 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................151

Figure 47: 88E1510 48-pin QFN Industrial Package Marking and Pin 1 Location...........................................151

Figure 48: 88E1512 56-pin QFN Industrial Package Marking and Pin 1 Location...........................................152

A Revision History .............................................................................................................................153

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 20 Document Classification: Public February 23, 2018

The RGMII supports 10/100/1000BASE-T modes of operation.

Table 4: RGMII

48-QFN

Pin #

Pin Name Pin

Type

Description

47 TX_CLK I RGMII Transmit Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance depending on speed.

2 TX_CTRL I RGMII Transmit Control. TX_EN is presented on the rising edge of TX_CLK.

A logical derivative of TX_EN and TX_ER is presented on the falling edge of

TX_CLK.

TXD[3]

TXD[2]

TXD[1]

TXD[0]

I RGMII Transmit Data.

TXD[3:0] run at double data rate with bits [3:0] of each byte to be transmitted

on the rising edge of TX_CLK, and bits [7:4] presented on the falling edge of

TX_CLK.

In 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on

the rising edge of TX_CLK.

40 RX_CLK O RGMII Receive Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance derived from the received data stream

depending on speed.

37 RX_CTRL O RGMII Receive Control. RX_DV is presented on the rising edge of RX_CLK.

A logical derivative of RX_DV and RX_ER is presented on the falling edge of

RX_CLK.

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O RGMII Receive Data. RXD[3:0] run at double data rate with bits [3:0] of each

byte received on the rising edge of RX_CLK, and bits [7:4] presented on the

falling edge of RX_CLK.

In 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on

the rising edge of RX_CLK.

Table 5: Management Interface and Interrupt

48-QFN

Pin #

Pin Name Pin

Type

Description

4 MDC I MDC is the management data clock reference for the serial management

interface. A continuous clock stream is not expected. The maximum frequency

supported is 12 MHz.

5 MDIO I/O MDIO is the management data. MDIO transfers management data in and out of

the device synchronously to MDC. This pin requires a pull-up resistor in a

range from 1.5 kΩ to 10 kΩ.

Table 6: LED Interface

48-QFN

Pin #

Pin Name Pin

Type

Description

10 LED[0] O LED output.

9 LED[1] I/O LED output

8 LED[2]/INTn O LED/Interrupt outputs.

LED[2] pin also functions as an active low interrupt pin.

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