EtronTech EM639165 SDRAM规格详解

EM639265

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"EM639265是EtronTech公司的一款8Mx16位同步动态随机存取内存(SDRAM)，适用于高速数据处理应用。该芯片具有快速访问时间、高时钟频率和完全同步操作特性。" 本文将详细讨论EM639265 SDRAM的主要特性和功能，以便于理解其在现代电子设备中的作用。 **主要特点** 1. **快速访问时间**: EM639265的访问时间非常快，范围为4.5/5/5.4纳秒，这意味着数据可以迅速从存储器中读取或写入，提高了系统的响应速度。 2. **高速时钟频率**: 支持200/166/143MHz的时钟频率，这使得芯片能够处理大量数据流，适合于需要高速处理的计算任务。 3. **全同步操作**: 内部采用流水线架构，所有操作都与系统时钟同步，提高了整体系统的效率和稳定性。 4. **内部结构**: 设计为2M字x16位x4银行，这种布局允许并行处理多个数据请求，从而提高内存带宽。 5. **可编程模式寄存器**: 提供了灵活性，用户可以设置CAS延迟（2或3）、突发长度（1,2,4,8,或全页）、突发类型（顺序或交织）以及突发停止功能，以适应不同应用场景。 6. **自动刷新和自刷新功能**: 自动刷新确保数据在长时间未访问后仍保持有效，而自刷新则在低功耗模式下维持内存状态。 7. **刷新周期**: 每64毫秒执行4096次刷新，这是SDRAM保持数据完整性的关键机制。 8. **电源管理**: 单一+3.3V电源，±0.3V公差，且支持CKE电源下降模式，以降低待机功耗。 9. **工作温度**: 能够在工业级温度范围内(-40~85°C)稳定工作，增加了其在恶劣环境下的适用性。 10. **接口**: 使用LVTTL（低电压晶体管-晶体管逻辑）接口，兼容多种系统设计。 11. **封装选项**: 提供54-pin 400mil塑料TSOPII封装和54-ball 8.0x8.0x1.2mm(max) FBGA封装，两种封装都是无铅和无卤素的，符合环保标准。 **应用场景** EM639265 SDRAM适用于需要高性能内存的多种设备，如嵌入式系统、个人计算机、服务器、网络设备和图形处理器等。其高速特性和灵活的配置选项使其成为系统设计者在内存选择上的理想选择，特别是在对延迟敏感的应用中。总结，EM639265是一款高性能的同步DRAM，它的快速访问时间、高时钟频率、同步操作、灵活的配置选项以及工业级温度范围使其成为各种高需求应用的理想内存解决方案。结合其多种封装选项和环保特性，这款芯片为设计者提供了强大且可靠的内存解决方案。

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EtronTech

EM639165

Rev. 2.3

Dec. /2013

CLK

COMMAND

T1 T2 T3 T4 T5 T6

NOP NOP READ A NOP NOP WRITE B NOP NOP

T7 T8

NOP

DQM

DIN B

CAS# Latency=2

CK2

, DQ

Must be Hi-Z before

the Write Command

Don’t Care

Figure 8. Read to Write Interval

(Burst Length ≥ 4, CAS# Latency = 2)

CLK

COMMAND

T1 T2 T3 T4 T5 T6

NOP READ A NOP NOP NOP NOP WRITE B NOP

T7 T8

NOP

DQM

DOUT A

DIN B

CAS# Latency=3

CK3

, DQ

Must be Hi-Z before

the Write Command

Don’t Care

Figure 9. Read to Write Interval

(Burst Length

≧

4, CAS# Latency = 3)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/

PrechargeAll command to the same bank. The following figure shows the optimum time that

BankPrecharge/ PrechargeAll command is issued in different CAS latency.

CLK

COMMAND

T1 T2 T3 T4 T5 T6

READ A NOP NOP NOP

Precharge

NOP NOP Activate

T7 T8

NOP

CAS# Latency=2

CK2

, DQ

CAS# Latency=3

CK3

, DQ

DOUT A

ADDRESS

Bank,

Col A

Bank (s)

Bank

Row

Figure 10. Read to Precharge

(CAS# Latency = 2, 3)

5 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after the

read operation. Once this command is given, any subsequent command cannot occur within a time delay

of {t

(min.) + burst length}. At full-page burst, only the read operation is performed in this command and

the auto precharge function is ignored.

EtronTech

EM639165

Rev. 2.3

Dec. /2013

6 Write command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active row

in an active bank. The bank must be active for at least t

RCD

(min.) before the Write command is issued.

During write bursts, the first valid data-in element will be registered coincident with the Write command.

Subsequent data elements will be registered on each successive positive clock edge (refer to the

following figure). The DQs remain with high-impedance at the end of the burst unless another command

is initiated. The burst length and burst sequence are determined by the mode register, which is already

programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column

0 and continue).

CLK

T1 T2 T3 T4 T5 T6

DIN A

don’t care

T7 T8

COMMAND

NOP WRITE A NOP NOP NOP NOP NOP NOP NOP

The first data element and the write

are registered on the same clock edge

Figure 11. Burst Write Operation

(Burst Length = 4)

A write burst without the auto precharge function may be interrupted by a subsequent Write,

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming

from Write command can occur on any clock cycle following the previous Write command (refer to the

following figure).

CLK

T1 T2 T3 T4 T5 T6

DIN A

DIN B

T7 T8

COMMAND

NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP

Figure 12. Write Interrupted by a Write

(Burst Length = 4)

The Read command that interrupts a write burst without auto precharge function should be issued

one cycle after the clock edge in which the last data-in element is registered. In order to avoid data

contention, input data must be removed from the DQs at least one clock cycle before the first read data

appears on the outputs (refer to the following figure). Once the Read command is registered, the data

inputs will be ignored and writes will not be executed.

EtronTech

EM639165

Rev. 2.3

Dec. /2013

CLK

COMMAND

T1 T2 T3 T4 T5 T6

NOP WRITE A READ B NOP NOP NOP NOP NOP

T7 T8

NOP

CAS# Latency=2

CK2

, DQ

CAS# Latency=3

CK3

, DQ

DOUT B

DIN A

don’t care

DIN A

don’t care don’t care

Input data must be removed from the DQ at

least one clock cycle before the Read data

appears on the outputs to avoid data contention

Figure 13. Write Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge

function should be issued m cycles after the clock edge in which the last data-in element is registered,

where m equals t

rounded up to the next whole number. In addition, the DQM signals must be used

to mask input data, starting with the clock edge following the last data-in element and ending with the

clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).

CLK

COMMAND

T1 T2 T3 T4 T5 T6

WRITE NOP NOP

Precharge

NOP NOP Activate NOP

DQM

Don’t Care

ADDRESS

Bank

Col n

Bank (s)

ROW

DIN

N+1

Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.

Figure 14. Write to Precharge

7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8

= Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after the

write operation. Once this command is given, any subsequent command can not occur within a time

delay of {(burst length -1) + t

+ t

(min.)}. At full-page burst, only the write operation is performed in

this command and the auto precharge function is ignored.

CLK

T1 T2 T3 T4 T5 T6

DIN A

T7 T8

COMMAND

Bank A

Activate

NOP NOP

WRITE A

Auto Precharge

NOP NOP NOP NOP NOP

Bank A

Activate

DAL

Begin AutoPrecharge

Bank can be reactivated at

completion of t

DAL

Figure 15. Burst Write with Auto-Precharge

(Burst Length = 2)

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