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首页Freescale K60单片机参考手册:功能与配置详解
Freescale K60单片机参考手册:功能与配置详解
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"Freescale K60 数据手册提供了关于 MK60DN256ZVLL10, MK60DX256ZVLL10, MK60DN512ZVLL10 等型号单片机的详细信息,包括56个章节的深入讲解。文档编号为 K60P100M100SF2RM,更新于2011年11月。"
K60系列是Freescale Semiconductor公司推出的一款基于ARMCortex-M4内核的高性能微控制器。本手册旨在为用户详细介绍K60子家族的特性和功能,以帮助开发者理解和应用这些器件。以下是手册的主要内容概述:
第1章:关于本文档
1.1节中,文档的目的被定义为提供K60系列单片机的全面技术信息,以供设计者和工程师参考。本章还明确了目标读者群体,包括硬件和软件开发人员、系统架构师以及需要理解K60芯片功能的任何人。
1.2节介绍了文档中使用的各种约定,如数字系统、排版符号以及特殊术语的定义,以确保读者能准确理解文档中的技术信息。
第2章:介绍
2.1节给出了整个手册的总体概述,而2.2节则专门介绍了K60家族,强调了其在微控制器领域的创新和优势。
2.3节详细阐述了K60系列的模块功能类别:
- ARMCortex-M4核心模块 包括Cortex-M4处理器的特性,如浮点单元(FPU)和数字信号处理(DSP)指令。
- 系统模块 包括电源管理、中断控制器等关键组件。
- 内存和内存接口 涵盖闪存、SRAM以及其他存储接口。
- 时钟 描述了芯片的时钟生成和管理机制。
- 安全和完整性模块 提供了保护代码和数据安全的功能。
- 模拟模块 包括ADC、DAC和其他模拟电路。
- 定时器模块 如PWM、RTC等定时/计数功能。
- 通信接口 如SPI、I2C、UART、CAN、USB等。
- 人机接口 如GPIO、LCD控制器、键盘/触摸屏接口等。
- 可订购的部件号 列出了所有可用的K60系列芯片型号。
第3章:芯片配置
3.1节为引言,3.2节进一步探讨了ARMCortex-M4核心的配置选项,如工作频率、功耗模式、中断和调试支持等。
这些章节构成了对Freescale K60系列单片机的详尽指南,涵盖了从基础硬件配置到高级应用的所有方面,为开发人员提供了必要的工具来充分利用这些强大的微控制器。无论是初学者还是经验丰富的工程师,都能从中受益,提升项目的设计和实现能力。
Section Number Title Page
Chapter 20
Direct memory access multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................417
20.1.1 Overview......................................................................................................................................................417
20.1.2 Features........................................................................................................................................................418
20.1.3 Modes of operation......................................................................................................................................418
20.2 External signal description............................................................................................................................................419
20.3 Memory map/register definition...................................................................................................................................419
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................420
20.4 Functional description...................................................................................................................................................421
20.4.1 DMA channels with periodic triggering capability......................................................................................421
20.4.2 DMA channels with no triggering capability...............................................................................................424
20.4.3 "Always enabled" DMA sources.................................................................................................................424
20.5 Initialization/application information...........................................................................................................................425
20.5.1 Reset.............................................................................................................................................................425
20.5.2 Enabling and configuring sources................................................................................................................425
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................429
21.1.1 Block diagram..............................................................................................................................................429
21.1.2 Block parts...................................................................................................................................................430
21.1.3 Features........................................................................................................................................................432
21.2 Modes of operation.......................................................................................................................................................433
21.3 Memory map/register definition...................................................................................................................................433
21.3.1 Control Register (DMA_CR).......................................................................................................................448
21.3.2 Error Status Register (DMA_ES)................................................................................................................450
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................452
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................454
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................456
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Section Number Title Page
21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................457
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................458
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................459
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................460
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................461
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................462
21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................463
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................463
21.3.14 Error Register (DMA_ERR)........................................................................................................................466
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................468
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................470
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................471
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................472
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................472
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................473
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................474
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................475
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................476
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................476
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................477
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................477
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................478
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........479
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................480
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................482
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Section Number Title Page
21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................483
21.4 Functional description...................................................................................................................................................484
21.4.1 eDMA basic data flow.................................................................................................................................484
21.4.2 Error reporting and handling........................................................................................................................487
21.4.3 Channel preemption.....................................................................................................................................489
21.4.4 Performance.................................................................................................................................................489
21.5 Initialization/application information...........................................................................................................................493
21.5.1 eDMA initialization.....................................................................................................................................493
21.5.2 Programming errors.....................................................................................................................................495
21.5.3 Arbitration mode considerations..................................................................................................................496
21.5.4 Performing DMA transfers..........................................................................................................................496
21.5.5 Monitoring transfer descriptor status...........................................................................................................500
21.5.6 Dynamic programming................................................................................................................................502
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................505
22.1.1 Features........................................................................................................................................................505
22.1.2 Modes of Operation.....................................................................................................................................506
22.1.3 Block Diagram.............................................................................................................................................507
22.2 EWM Signal Descriptions............................................................................................................................................508
22.3 Memory Map/Register Definition.................................................................................................................................508
22.3.1 Control Register (EWM_CTRL).................................................................................................................508
22.3.2 Service Register (EWM_SERV)..................................................................................................................509
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................510
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................510
22.4 Functional Description..................................................................................................................................................511
22.4.1 The EWM_out Signal..................................................................................................................................511
22.4.2 The EWM_in Signal....................................................................................................................................512
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Section Number Title Page
22.4.3 EWM Counter..............................................................................................................................................512
22.4.4 EWM Compare Registers............................................................................................................................512
22.4.5 EWM Refresh Mechanism...........................................................................................................................513
Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction...................................................................................................................................................................515
23.2 Features.........................................................................................................................................................................515
23.3 Functional Overview.....................................................................................................................................................517
23.3.1 Unlocking and Updating the Watchdog.......................................................................................................518
23.3.2 The Watchdog Configuration Time (WCT).................................................................................................519
23.3.3 Refreshing the Watchdog.............................................................................................................................520
23.3.4 Windowed Mode of Operation....................................................................................................................520
23.3.5 Watchdog Disabled Mode of Operation......................................................................................................520
23.3.6 Low Power Modes of Operation..................................................................................................................521
23.3.7 Debug Modes of Operation..........................................................................................................................521
23.4 Testing the Watchdog...................................................................................................................................................522
23.4.1 Quick Test....................................................................................................................................................522
23.4.2 Byte Test......................................................................................................................................................522
23.5 Backup Reset Generator...............................................................................................................................................524
23.6 Generated Resets and Interrupts...................................................................................................................................524
23.7 Memory Map and Register Definition..........................................................................................................................525
23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................526
23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................528
23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................528
23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................529
23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................529
23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................530
23.7.7 Watchdog Refresh Register (WDOG_REFRESH)......................................................................................530
23.7.8 Watchdog Unlock Register (WDOG_UNLOCK).......................................................................................530
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Section Number Title Page
23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................531
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................531
23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................532
23.7.12 Watchdog Prescaler Register (WDOG_PRESC).........................................................................................532
23.8 Watchdog Operation with 8-bit access.........................................................................................................................532
23.8.1 General Guideline........................................................................................................................................532
23.8.2 Refresh and Unlock operations with 8-bit access........................................................................................533
23.9 Restrictions on Watchdog Operation............................................................................................................................534
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................537
24.1.1 Features........................................................................................................................................................537
24.1.2 Modes of Operation.....................................................................................................................................540
24.2 External Signal Description..........................................................................................................................................541
24.3 Memory Map/Register Definition.................................................................................................................................541
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................542
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................543
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................544
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................545
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................546
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................548
24.3.7 MCG Status Register (MCG_S)..................................................................................................................549
24.3.8 MCG Auto Trim Control Register (MCG_ATC)........................................................................................551
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................551
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................552
24.4 Functional Description..................................................................................................................................................552
24.4.1 MCG Mode State Diagram..........................................................................................................................552
24.4.2 Low Power Bit Usage..................................................................................................................................557
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