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首页联想i系列Intel Merom处理器LA-3541P电路图纸
联想i系列Intel Merom处理器LA-3541P电路图纸
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更新于2024-06-18
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这份文档是关于联想i系列产品的图纸,具体型号为LA-3541P。图纸标题为"Intel Merom处理器与Crestline+DDRII+ICH8M IFTxx Schematics Document",表明它详细展示了基于Intel Merom处理器架构的计算机设计,包括 Crestline高速内存控制器、DDR II内存接口以及ICH8M芯片组的电路布局和连接。该图纸由Compal Electronics, Inc. 所制作,体现了公司对知识产权的重视,所有图纸内容均为保密性质,只能在公司内部研发部门授权的情况下流转,未经书面许可,不得向第三方透露或使用。 文档的版本为0.1,最早发行日期为2006年11月1日,且在2006年8月18日进行了解码,并在2007年8月18日更新了 deciphered date(可能是解密或翻译日期)。图纸的大小没有直接给出,但可以推测它可能包含多张图纸,因为有"Sheet of"的提及,每张图纸都有对应的编号,从1到4。安全分类为Compal Confidential,强调了图纸中的技术信息对于Compal Electronics, Inc. 是专有的商业秘密。 这份图纸可能包含了硬件设计细节,如主板布局、组件位置、电源管理、信号路径、散热设计等内容,对于理解联想i系列电脑内部结构、优化性能或是进行维修和升级具有重要意义。由于涉及到英特尔的处理器技术,还可能涉及到了BIOS设置、内存管理、PCI-E接口等关键模块的配置和规格。整体而言,这是一份高度专业且敏感的工程图纸,需在合法授权的范围内使用。
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![](https://csdnimg.cn/release/download_crawler_static/88673019/bg8.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_ITX_MRX_N0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P0
DMI_ITX_MRX_P3
DMI_ITX_MRX_P2
DMI_MTX_IRX_P1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P3
DMI_MTX_IRX_P2
DMI_ITX_MRX_N3
DMI_ITX_MRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_N1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N2
DMI_ITX_MRX_N1
CLK_MCH_3GPLL
SMRCOMP
SMRCOMP#
MCH_CLKSEL1
MCH_CLKSEL2
MCH_CLKSEL0
PM_EXTTS#0
GMCH_PWROK
MCH_CLKREQ#
CLK_MCH_3GPLL#
GMCH_PWROK
ICH_POK
VGATE
SM_RCOMP_VOL
SM_RCOMP_VOH
SM_RCOMP_VOH
SM_RCOMP_VOL
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
MCH_CFG_13
MCH_CFG_20
MCH_CFG_9
MCH_CFG_16
MCH_CFG_12
MCH_CFG_19
MCH_CFG_5
MCH_TEST_1
MCH_TEST_2
CL_VREF
PM_EXTTS#1
MCH_RSTIN#
PM_EXTTS#1
PM_EXTTS#0
MCH_CLKREQ#
DDRA_SMA14
DDRB_SMA14
SM_RCOMP_VOH
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M#
CLK_DREF_96M
SM_VREF
CLK_DREF_96M#
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_SSC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MCH_CLKREQ# <16>
PM_BMBUSY#<22>
CLK_MCH_3GPLL# <16>
CLK_MCH_3GPLL <16>
H_THERMTRIP#<4,21>
MCH_ICH_SYNC# <22>
MCH_CLKSEL2<16>
MCH_CLKSEL0<16>
PM_EXTTS#0<14>
PM_DPRSLPVR<22,51>
MCH_CLKSEL1<16>
VGATE<22,51>
ICH_POK<22,34>
DDRA_CLK0 <14>
DDRA_CLK1 <14>
DDRB_CLK0 <15>
DDRB_CLK1 <15>
DDRA_CLK0# <14>
DDRA_CLK1# <14>
DDRB_CLK0# <15>
DDRB_CLK1# <15>
DDRA_CKE0 <14>
DDRA_CKE1 <14>
DDRB_CKE0 <15>
DDRB_CKE1 <15>
DDRA_SCS0# <14>
DDRA_SCS1# <14>
DDRB_SCS0# <15>
DDRB_SCS1# <15>
DDRA_ODT0 <14>
DDRA_ODT1 <14>
DDRB_ODT0 <15>
DDRB_ODT1 <15>
DMI_ITX_MRX_N0 <22>
DMI_ITX_MRX_N1 <22>
DMI_ITX_MRX_N2 <22>
DMI_ITX_MRX_N3 <22>
DMI_ITX_MRX_P0 <22>
DMI_ITX_MRX_P1 <22>
DMI_ITX_MRX_P2 <22>
DMI_ITX_MRX_P3 <22>
DMI_MTX_IRX_N0 <22>
DMI_MTX_IRX_N1 <22>
DMI_MTX_IRX_N2 <22>
DMI_MTX_IRX_N3 <22>
DMI_MTX_IRX_P0 <22>
DMI_MTX_IRX_P1 <22>
DMI_MTX_IRX_P2 <22>
DMI_MTX_IRX_P3 <22>
CL_CLK0 <22>
CL_DATA0 <22>
CL_PWROK <22>
CL_RST# <22>
PM_EXTTS#1<15>
H_DPRSTP#<5,21,51>
PLT_RST#<20,22,29,30,41>
DDRA_SMA14<14>
DDRB_SMA14<14,15>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
+1.8V
+1.8V
+1.8V
+3VS
+1.25VS
+3VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
IFTXX M/B LA-3541P Schematic
0
Crestline (2/7)-DMI/DDR
Custom
852Wednesday, November 01, 2006
2006/08/18 2007/8/18
Compal Electronics, Inc.
CFG[13:12]
1 = PCIE/SDVO are operating simu.
CFG19
(Default)
CFG20
0 = DMI x 2
*
Strap Pin Table
*
10 = All Z Mode Enabled
(Default)
1 = Normal Operation
CFG5
SDVO_CTRLDATA
1 = DMI Lane Reversal Enable
*
1 = Dynamic ODT Enabled
(Default)
*
(Default)
00 = Reserved
*
1 = DMI x 4
0 = No SDVO Device Present
(Default)
*
*
(Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
010 = 800MT/s FSB
CFG16
011 = 667MT/s FSB
0 = Lane Reversal Enable
CFG9
1 = SDVO Device Present
CFG[2:0]
11 = Normal Operation
20mil
Use VGATE for GMCH_PWROK
If THERMTRIP no used, left NC
9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47
Layout Note:
SM_VREF trace
width and spacing
is 20/20.
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
R530 4.02K_0402_1%@
R534 10K_0402_5%
R517 20_0402_1%
1 2
R514
3.01K_0402_1%
R518
1K_0402_1%
1 2
C636
0.01U_0402_16V7K
C637
2.2U_0805_10V6K
R513
1K_0402_1%
R575 0_0402_5%PM@
1 2
PM
MISC
NC
DDR MUXINGCLK
DMI
CFGRSVD
GRAPHICS VID
ME
U37B
CRESTLINE_1p0
PM@
SM_CK_0
AV29
SM_CK_1
BB23
RSVD28
BF23
SM_CK_3
BA25
SM_CK#_0
AW30
SM_CK#_1
BA23
RSVD29
BG23
SM_CK#_3
AW25
SM_CKE_0
BE29
SM_CKE_1
AY32
SM_CKE_3
BD39
SM_CKE_4
BG37
SM_CS#_0
BG20
SM_CS#_1
BK16
SM_CS#_2
BG16
SM_CS#_3
BE13
RSVD34
BH39
SM_ODT_0
BH18
SM_ODT_1
BJ15
SM_ODT_2
BJ14
SM_ODT_3
BE16
SM_RCOMP
BL15
SM_RCOMP#
BK14
SM_VREF_0
AR49
SM_VREF_1
AW4
CFG_18
L32
CFG_19
N33
CFG_2
N24
CFG_0
P27
CFG_1
N27
CFG_20
L35
CFG_3
C21
CFG_4
C23
CFG_5
F23
CFG_6
N23
CFG_7
G23
CFG_8
J20
CFG_9
C20
CFG_10
R24
CFG_11
L23
CFG_12
J23
CFG_13
E23
CFG_14
E20
CFG_15
K23
CFG_16
M20
CFG_17
M24
PM_BM_BUSY#
G41
PM_EXT_TS#_0
L36
PM_EXT_TS#_1
J36
PWROK
AW49
RSTIN#
AV20
DPLL_REF_CLK
B42
DPLL_REF_CLK#
C42
DPLL_REF_SSCLK
H48
DPLL_REF_SSCLK#
H47
DMI_RXN_0
AN47
DMI_RXN_1
AJ38
DMI_RXN_2
AN42
DMI_RXN_3
AN46
DMI_RXP_0
AM47
DMI_RXP_1
AJ39
DMI_RXP_2
AN41
DMI_RXP_3
AN45
DMI_TXN_0
AJ46
DMI_TXN_1
AJ41
DMI_TXN_2
AM40
DMI_TXN_3
AM44
DMI_TXP_0
AJ47
DMI_TXP_1
AJ42
DMI_TXP_2
AM39
DMI_TXP_3
AM43
RSVD10
AR37
RSVD12
AL36
RSVD11
AM36
RSVD13
AM37
RSVD22
BJ20
RSVD23
BK22
RSVD24
BF19
RSVD25
BH20
RSVD26
BK18
PM_DPRSTP#
L39
SM_CK_4
AV23
SM_CK#_4
AW23
RSVD30
BC23
RSVD31
BD24
RSVD35
AW20
RSVD36
BK20
RSVD5
AR12
RSVD6
AR13
RSVD7
AM12
RSVD8
AN13
RSVD1
P36
RSVD2
P37
RSVD3
R35
RSVD4
N35
GFX_VID_0
E35
GFX_VID_1
A39
GFX_VID_2
C38
GFX_VID_3
B39
GFX_VR_EN
E36
RSVD27
BJ18
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
THERMTRIP#
N20
DPRSLPVR
G36
RSVD9
J12
CL_CLK
AM49
CL_DATA
AK50
CL_PWROK
AT43
CL_RST#
AN49
CL_VREF
AM50
LVDSA_DATA#_3
C48
LVDSA_DATA_3
D47
RSVD39
B44
RSVD40
C44
SA_MA_14
BJ29
SB_MA_14
BE24
RSVD21
B51
NC_1
BJ51
NC_2
BK51
NC_3
BK50
NC_4
BL50
NC_5
BL49
NC_6
BL3
NC_7
BL2
NC_8
BK1
NC_9
BJ1
NC_10
E1
NC_11
A5
NC_12
C51
NC_13
B50
NC_14
A50
NC_15
A49
SDVO_CTRL_CLK
H35
SDVO_CTRL_DATA
K36
CLK_REQ#
G39
RSVD14
D20
ICH_SYNC#
G40
RSVD20
H10
RSVD41
A35
RSVD42
B37
RSVD43
B36
RSVD44
B34
RSVD45
C34
PEG_CLK#
K45
PEG_CLK
K44
TEST_1
A37
NC_16
BK2
TEST_2
R32
R525 100_0402_5%
R536 10K_0402_5%
R523 4.02K_0402_1%@
R516 20_0402_1%
1 2
R524 4.02K_0402_1%@
R528
1K_0402_1%
1 2
R576 0_0402_5%PM@
1 2
R532 10K_0402_5%
R535 0_0402_5%
1 2
R537 0_0402_5%
R521 4.02K_0402_1%@
R578 0_0402_5%@
1 2
C639
0.1U_0402_16V4Z
1
2
R538 20K_0402_5%
R515
1K_0402_1%
C640
0.1U_0402_16V4Z
1
2
R577 0_0402_5%PM@
1 2
R522 4.02K_0402_1%@
R527 0_0402_5%
1 2
R579 0_0402_5%@
1 2
R526 4.02K_0402_1%@
R533 0_0402_5%@
1 2
R531
392_0402_1%
1 2
R520
1K_0402_1%
1 2
C635
2.2U_0805_10V6K
R529 4.02K_0402_1%@
C638
0.01U_0402_16V7K
R574 0_0402_5%PM@
1 2
![](https://csdnimg.cn/release/download_crawler_static/88673019/bg9.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRB_SMA3
DDRB_SMA7
DDRB_SMA0
DDRB_SMA2
DDRB_SMA10
DDRB_SMA1
DDRB_SMA6
DDRB_SMA5
DDRB_SMA12
DDRB_SMA11
DDRB_SMA4
DDRB_SMA8
DDRB_SMA9
DDRB_SMA13
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ7
DDRB_SDQ6
DDRB_SDQ5
DDRB_SDQ4
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ12
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ13
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ22
DDRB_SDQ21
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ23
DDRB_SDQ16
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
DDRB_SDQ27
DDRB_SDQ26
DDRB_SDQ29
DDRB_SDQ31
DDRB_SDQ30
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ0
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ28
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRA_SDQ1
DDRA_SDQ7
DDRA_SDQ6
DDRA_SDQ5
DDRA_SDQ4
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ12
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ13
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ22
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ23
DDRA_SDQ16
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ27
DDRA_SDQ26
DDRA_SDQ29
DDRA_SDQ31
DDRA_SDQ30
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ28
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SMA3
DDRA_SMA7
DDRA_SMA0
DDRA_SMA2
DDRA_SMA10
DDRA_SMA1
DDRA_SMA6
DDRA_SMA5
DDRA_SMA12
DDRA_SMA11
DDRA_SMA4
DDRA_SMA8
DDRA_SMA9
DDRA_SMA13
DDRB_SDQ[0..63]
DDRB_SMA[0..13]
DDRB_SDM[0..7]
DDRB_SDQS0
DDRB_SDQS5
DDRB_SDQS4
DDRB_SDM6
DDRB_SDM1
DDRB_SDM5
DDRB_SDM0
DDRB_SDM4
DDRB_SDM3
DDRB_SDM7
DDRB_SDM2
DDRB_SDQS3
DDRB_SDQS7
DDRB_SDQS2
DDRB_SDQS6
DDRB_SDQS1
DDRB_SDQS5#
DDRB_SDQS0#
DDRB_SDQS4#
DDRB_SDQS3#
DDRB_SDQS7#
DDRB_SDQS2#
DDRB_SDQS6#
DDRB_SDQS1#
DDRA_SDQS5
DDRA_SDQS0
DDRA_SDQS4
DDRA_SDQS3
DDRA_SDQS7
DDRA_SDQS2
DDRA_SDQS6
DDRA_SDQS1
DDRA_SDQS5#
DDRA_SDQS0#
DDRA_SDQS4#
DDRA_SDQS3#
DDRA_SDQS7#
DDRA_SDQS2#
DDRA_SDQS6#
DDRA_SDQS1#
DDRA_SDQ[0..63]
DDRA_SMA[0..13]
DDRA_SDM[0..7]
DDRA_SDM6
DDRA_SDM5
DDRA_SDM0
DDRA_SDM4
DDRA_SDM1
DDRA_SDM7
DDRA_SDM2
DDRA_SDM3
SA_RCVEN#
SB_RCVEN#
DDRA_SBS2 <14>
DDRA_SBS0 <14>
DDRA_SBS1 <14>
DDRA_SDQS6 <14>
DDRA_SDQS3 <14>
DDRA_SDQS6# <14>
DDRA_SDQS3# <14>
DDRA_SDQS7# <14>
DDRA_SDQS5# <14>
DDRA_SDQS0# <14>
DDRA_SDQS4# <14>
DDRA_SDQS1# <14>
DDRA_SDQS2# <14>
DDRA_SDQ[0..63]<14>
DDRA_SMA[0..13]<14>
DDRA_SDM[0..7]<14>
DDRA_SDQS7 <14>
DDRA_SDQS5 <14>
DDRB_SDQ[0..63]<15>
DDRB_SMA[0..13]<15>
DDRB_SDM[0..7]<15>
DDRA_SDQS0 <14>
DDRA_SWE# <14>
DDRA_SDQS4 <14>
DDRB_SWE# <15>
DDRA_SDQS1 <14>
DDRB_SBS2 <15>
DDRB_SBS0 <15>
DDRB_SBS1 <15>
DDRA_SDQS2 <14>
DDRB_SDQS6 <15>
DDRB_SDQS3 <15>
DDRB_SDQS6# <15>
DDRB_SDQS3# <15>
DDRB_SDQS7# <15>
DDRB_SDQS5# <15>
DDRB_SDQS0# <15>
DDRB_SDQS4# <15>
DDRB_SDQS1# <15>
DDRB_SDQS2# <15>
DDRB_SDQS7 <15>
DDRB_SDQS5 <15>
DDRB_SDQS0 <15>
DDRB_SDQS4 <15>
DDRB_SDQS1 <15>
DDRB_SDQS2 <15>
DDRA_SCAS# <14>
DDRA_SRAS# <14>
DDRB_SCAS# <15>
DDRB_SRAS# <15>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
IFTXX M/B LA-3541P Schematic
0
Crestline (3/7)-DDRII
B
952Wednesday, November 01, 2006
2006/08/18 2007/8/18
Compal Electronics, Inc.
T18
PAD
DDR SYSTEM MEMORY B
U37E
CRESTLINE_1p0
PM@
SB_DQ_0
AP49
SB_DQ_1
AR51
SB_DQ_10
BA49
SB_DQ_11
BE50
SB_DQ_12
BA51
SB_DQ_13
AY49
SB_DQ_14
BF50
SB_DQ_15
BF49
SB_DQ_16
BJ50
SB_DQ_17
BJ44
SB_DQ_18
BJ43
SB_DQ_19
BL43
SB_DQ_2
AW50
SB_DQ_20
BK47
SB_DQ_21
BK49
SB_DQ_22
BK43
SB_DQ_23
BK42
SB_DQ_24
BJ41
SB_DQ_25
BL41
SB_DQ_26
BJ37
SB_DQ_27
BJ36
SB_DQ_28
BK41
SB_DQ_29
BJ40
SB_DQ_3
AW51
SB_DQ_30
BL35
SB_DQ_31
BK37
SB_DQ_32
BK13
SB_DQ_33
BE11
SB_DQ_34
BK11
SB_DQ_35
BC11
SB_DQ_36
BC13
SB_DQ_37
BE12
SB_DQ_38
BC12
SB_DQ_39
BG12
SB_DQ_4
AN51
SB_DQ_40
BJ10
SB_DQ_41
BL9
SB_DQ_42
BK5
SB_DQ_43
BL5
SB_DQ_44
BK9
SB_DQ_45
BK10
SB_DQ_46
BJ8
SB_DQ_47
BJ6
SB_DQ_48
BF4
SB_DQ_49
BH5
SB_DQ_5
AN50
SB_DQ_50
BG1
SB_DQ_51
BC2
SB_DQ_52
BK3
SB_DQ_53
BE4
SB_DQ_54
BD3
SB_DQ_55
BJ2
SB_DQ_56
BA3
SB_DQ_57
BB3
SB_DQ_58
AR1
SB_DQ_59
AT3
SB_DQ_6
AV50
SB_DQ_60
AY2
SB_DQ_61
AY3
SB_DQ_62
AU2
SB_DQ_63
AT2
SB_DQ_7
AV49
SB_DQ_8
BA50
SB_DQ_9
BB50
SB_BS_0
AY17
SB_BS_1
BG18
SB_BS_2
BG36
SB_CAS#
BE17
SB_DM_0
AR50
SB_DM_1
BD49
SB_DM_2
BK45
SB_DM_3
BL39
SB_DM_4
BH12
SB_DM_5
BJ7
SB_DM_6
BF3
SB_DM_7
AW2
SB_DQS_0
AT50
SB_DQS_1
BD50
SB_DQS_2
BK46
SB_DQS_3
BK39
SB_DQS_4
BJ12
SB_DQS_5
BL7
SB_DQS_6
BE2
SB_DQS_7
AV2
SB_DQS#_0
AU50
SB_DQS#_1
BC50
SB_DQS#_2
BL45
SB_DQS#_3
BK38
SB_DQS#_4
BK12
SB_DQS#_5
BK7
SB_DQS#_6
BF2
SB_DQS#_7
AV3
SB_MA_0
BC18
SB_MA_1
BG28
SB_MA_10
BG17
SB_MA_11
BE37
SB_MA_12
BA39
SB_MA_13
BG13
SB_MA_2
BG25
SB_MA_3
AW17
SB_MA_4
BF25
SB_MA_5
BE25
SB_MA_6
BA29
SB_MA_7
BC28
SB_MA_8
AY28
SB_MA_9
BD37
SB_RAS#
AV16
SB_RCVEN#
AY18
SB_WE#
BC17
T17
PAD
DDR SYSTEM MEMORY A
U37D
CRESTLINE_1p0
PM@
SA_DQ_0
AR43
SA_DQ_1
AW44
SA_DQ_10
BG47
SA_DQ_11
BJ45
SA_DQ_12
BB47
SA_DQ_13
BG50
SA_DQ_14
BH49
SA_DQ_15
BE45
SA_DQ_16
AW43
SA_DQ_17
BE44
SA_DQ_18
BG42
SA_DQ_19
BE40
SA_DQ_2
BA45
SA_DQ_20
BF44
SA_DQ_21
BH45
SA_DQ_22
BG40
SA_DQ_23
BF40
SA_DQ_24
AR40
SA_DQ_25
AW40
SA_DQ_26
AT39
SA_DQ_27
AW36
SA_DQ_28
AW41
SA_DQ_29
AY41
SA_DQ_3
AY46
SA_DQ_30
AV38
SA_DQ_31
AT38
SA_DQ_32
AV13
SA_DQ_33
AT13
SA_DQ_34
AW11
SA_DQ_35
AV11
SA_DQ_36
AU15
SA_DQ_37
AT11
SA_DQ_38
BA13
SA_DQ_39
BA11
SA_DQ_4
AR41
SA_DQ_40
BE10
SA_DQ_41
BD10
SA_DQ_42
BD8
SA_DQ_43
AY9
SA_DQ_44
BG10
SA_DQ_45
AW9
SA_DQ_46
BD7
SA_DQ_47
BB9
SA_DQ_48
BB5
SA_DQ_49
AY7
SA_DQ_5
AR45
SA_DQ_50
AT5
SA_DQ_51
AT7
SA_DQ_52
AY6
SA_DQ_53
BB7
SA_DQ_54
AR5
SA_DQ_55
AR8
SA_DQ_56
AR9
SA_DQ_57
AN3
SA_DQ_58
AM8
SA_DQ_59
AN10
SA_DQ_6
AT42
SA_DQ_60
AT9
SA_DQ_61
AN9
SA_DQ_62
AM9
SA_DQ_63
AN11
SA_DQ_7
AW47
SA_DQ_8
BB45
SA_DQ_9
BF48
SA_BS_0
BB19
SA_BS_1
BK19
SA_BS_2
BF29
SA_CAS#
BL17
SA_DM_0
AT45
SA_DM_1
BD44
SA_DM_2
BD42
SA_DM_3
AW38
SA_DM_4
AW13
SA_DM_5
BG8
SA_DM_6
AY5
SA_DQS_0
AT46
SA_DQS_1
BE48
SA_DQS_2
BB43
SA_DQS_3
BC37
SA_DQS_4
BB16
SA_DQS_5
BH6
SA_DQS_6
BB2
SA_DQS_7
AP3
SA_DM_7
AN6
SA_DQS#_0
AT47
SA_DQS#_1
BD47
SA_DQS#_2
BC41
SA_DQS#_3
BA37
SA_DQS#_4
BA16
SA_DQS#_5
BH7
SA_DQS#_6
BC1
SA_DQS#_7
AP2
SA_MA_0
BJ19
SA_MA_1
BD20
SA_MA_10
BC19
SA_MA_11
BE28
SA_MA_12
BG30
SA_MA_13
BJ16
SA_MA_2
BK27
SA_MA_3
BH28
SA_MA_4
BL24
SA_MA_5
BK28
SA_MA_6
BJ27
SA_MA_7
BJ25
SA_MA_8
BL28
SA_MA_9
BA28
SA_RAS#
BE18
SA_RCVEN#
AY20
SA_WE#
BA19
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