Parameter Details Notes
Processor Type Y-Processor Line
Data Burst Length 8 8
DRAM Device Bank Support 8 8
Notes: 1. DDR3L = Low Voltage Double Data Rate 3, DDR3L-RS = Low Voltage Double Data Rate 3 Reduced Stand-by,
LPDDR3 = Low Power Double Data Rate 3
2. Raw Card A = Dual Ranked x16 unbuffered, Raw Card B = Single Ranked x8 unbuffered, Raw Card C = Single
Ranked x16 unbuffered, Raw Card F = Dual Ranked x8 unbuffered
3. SDP = Single Die Package, DDP = Dual Die Package, QDP = Quad Die Package
4. Command 0.5N Mode indicates a new command may be transferred on both the positive and negative edges of the
clock, Command 1N Mode indicates a new command may be issued every clock, and Command 2N Mode indicates
a new command may be issued every 2 clocks.
5. The side-by-side ball map placement, also called "Non-Interleaved", where each memory channel's DQ/DQS/DQS#
signals are grouped together on one side of the processor package. Interleaved processor Memory ball map is
where the Channel 0 strobe and data balls are grouped along the outer perimeter and the Channel 1 strobe and
data balls are grouped along the inner part of the ball map.
6. tCL = CAS Latency, tRCD = Activate Command to READ or WRITE Command delay, tRP = PRECHARGE Command
Period, CWL = CAS Write Latency, tCK = Clock Cycle
7. The System Memory Controller generated DRAM device side Reference Voltage for the DQ Input Receivers
(VREFDQ) and the Reference Voltage for the Command and Control Input Receivers (VREFCA) for both system
memory interface channels.
8. Max Capacity (GB) = (DRAM Die Gb Technology * Total Number of DRAM Dies) / 8
a. Memory Down Example:
i. Channel A = LPDDR3 QDP 2-16-32 = 2 QDP DRAM 16Gb Packages = 8 Total DRAM 4Gb Dies
ii. Channel B = LPDDR3 QDP 2-16-32 = 2 QDP DRAM 16Gb Packages = 8 Total DRAM 4Gb Dies
iii. Maximum Capacity (GB) = ( 4Gb * (8 + 8) ) / 8 = 8 GB
9. Theoretical Maximum Bandwidth (GB/s) = ( ( Transfer Rate * Number of Memory Channels * Channel Data Bits ) /
8 ) / 1000
a. 1333 Example: = ( ( 1333 * 2 * 64 ) / 8 ) / 1000 = 21.3 GB/s
b. 1600 Example: = ( ( 1600 * 2 * 64 ) / 8 ) / 1000 = 25.6 GB/s
System Memory Organization Modes
The system memory controller supports two memory organization modes – single-
channel and dual-channel. Depending on how the DIMM Modules or DRAM Down
Devices are configured in each memory channel, a number of different configurations
can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B are populated in any order, but not both.
Dual-Channel Mode – Intel
®
Flex Memory Technology Mode
The system memory controller supports Intel Flex Memory Technology Mode where
memory is divided into a symmetric and asymmetric zone. The symmetric zone starts
at the lowest address in each channel and is contiguous until the asymmetric zone
begins or until the top address of the channel with the smaller capacity is reached. In
this mode, the system runs with one zone of dual-channel mode and one zone of
single-channel mode, simultaneously, across the entire memory array. This mode is
used when both Channel A and Channel B are populated with memory but the total
amount of memory in each channel is not the same.
Note:
Channels A and B can be mapped for Physical Channel 0 and 1 respectively or vice
versa; however, the Channel A size must be greater or equal to the Channel B size.
2.1.2
Interfaces—Processor
Intel
®
Core
™
M Processor Family
September 2014 Datasheet – Volume 1 of 2
Order No.: 330834-001v1 17