5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALINX Confidential
www.alinx.com
+1.2V
VRP_64
PL_DDR4_A0
PL_DDR4_CLK_P
PL_DDR4_CLK_N
PL_CLK0_P
PL_CLK0_N
PL_CLK0_N
PL_CLK0_P
PL_DDR4_DM1
PL_DDR4_DQ0
PL_DDR4_DQ7
PL_DDR4_DQ6
PL_DDR4_DQS0_P
PL_DDR4_DQ1
PL_DDR4_DQS0_N
PL_DDR4_DQ2
PL_DDR4_DQ5
PL_DDR4_DQ4
PL_DDR4_DQ3
PL_DDR4_DM0
PL_DDR4_DQ15
PL_DDR4_DQ14
PL_DDR4_DQ13
PL_DDR4_DQ12
PL_DDR4_DQ11
PL_DDR4_DQ10
PL_DDR4_DQ9
PL_DDR4_DQ8
PL_DDR4_DQS1_P
PL_DDR4_DQS1_N
PL_DDR4_OTD
PL_DDR4_A6
PL_DDR4_BA1
PL_DDR4_A9
PL_DDR4_A5
PL_DDR4_CS_B
PL_DDR4_BA0
PL_DDR4_A13
PL_DDR4_A7
PL_DDR4_CAS_B
PL_DDR4_ACT_B
PL_DDR4_A4
PL_DDR4_A12
PL_DDR4_BG0
PL_DDR4_WE_B
PL_DDR4_A8
PL_DDR4_A10
PL_DDR4_A3
PL_DDR4_RST
PL_DDR4_CKE
PL_DDR4_RAS_B
PL_DDR4_A2
PL_DDR4_A11
PL_DDR4_A1
PLDDR4_1V2
PL_DDR4_A0
15
PL_DDR4_CLK_P
15
PL_DDR4_CLK_N
15
PL_CLK0_P
17
PL_CLK0_N
17
PL_DDR4_DM1
15
PL_DDR4_DQ0
15
PL_DDR4_DQ7
15
PL_DDR4_DQ6
15
PL_DDR4_DQS0_P
15
PL_DDR4_DQ1
15
PL_DDR4_DQS0_N
15
PL_DDR4_DQ2
15
PL_DDR4_DQ5
15
PL_DDR4_DQ4
15
PL_DDR4_DQ3
15
PL_DDR4_DM0
15
PL_DDR4_DQ15
15
PL_DDR4_DQ14
15
PL_DDR4_DQ13
15
PL_DDR4_DQ12
15
PL_DDR4_DQ11
15
PL_DDR4_DQ10
15
PL_DDR4_DQ9
15
PL_DDR4_DQ8
15
PL_DDR4_DQS1_P
15
PL_DDR4_DQS1_N
15
PL_DDR4_OTD
15
PL_DDR4_A6
15
PL_DDR4_BA1
15
PL_DDR4_A9
15
PL_DDR4_A5
15
PL_DDR4_CS_B
15
PL_DDR4_BA0
15
PL_DDR4_A13
15
PL_DDR4_A7
15
PL_DDR4_CAS_B
15
PL_DDR4_ACT_B
15
PL_DDR4_A4
15
PL_DDR4_A12
15
PL_DDR4_BG0
15
PL_DDR4_WE_B
15
PL_DDR4_A8
15
PL_DDR4_A10
15
PL_DDR4_A3
15
PL_DDR4_RST
15
PL_DDR4_CKE
15
PL_DDR4_RAS_B
15
PL_DDR4_A2
15
PL_DDR4_A11
15
PL_DDR4_A1
15
Title
Size
Document Number Rev
Date: Sheet
of
ACU4EV核心板 Schematics
1.0
PAGE05 Z7 Bank64
521Tuesday, March 10, 2020
Title
Size
Document Number Rev
Date: Sheet
of
ACU4EV核心板 Schematics
1.0
PAGE05 Z7 Bank64
521Tuesday, March 10, 2020
Title
Size
Document Number Rev
Date: Sheet
of
ACU4EV核心板 Schematics
1.0
PAGE05 Z7 Bank64
521Tuesday, March 10, 2020
R51 1K 1%
C54
100uF
BANK64
XCZU4EV-SFVC784-1
U3-12
IO_T0U_N12_VRP_64
AD6
IO_T1U_N12_64
AH6
IO_T2U_N12_64
AB5
IO_T3U_N12_64
AE4
IO_L1N_T0L_N1_DBC_64
AD9
IO_L1P_T0L_N0_DBC_64
AC9
IO_L2N_T0L_N3_64
AE8
IO_L2P_T0L_N2_64
AE9
IO_L3N_T0L_N5_AD15N_64
AC8
IO_L3P_T0L_N4_AD15P_64
AB8
IO_L4N_T0U_N7_DBC_AD7N_64
AE7
IO_L4P_T0U_N6_DBC_AD7P_64
AD7
IO_L5N_T0U_N9_AD14N_64
AC7
IO_L5P_T0U_N8_AD14P_64
AB7
IO_L6N_T0U_N11_AD6N_64
AC6
IO_L6P_T0U_N10_AD6P_64
AB6
IO_L7N_T1L_N1_QBC_AD13N_64
AH9
IO_L7P_T1L_N0_QBC_AD13P_64
AG9
IO_L8N_T1L_N3_AD5N_64
AG8
IO_L8P_T1L_N2_AD5P_64
AF8
IO_L9N_T1L_N5_AD12N_64
AH7
IO_L9P_T1L_N4_AD12P_64
AH8
IO_L10N_T1U_N7_QBC_AD4N_64
AG5
IO_L10P_T1U_N6_QBC_AD4P_64
AG6
IO_L11N_T1U_N9_GC_64
AF6
IO_L11P_T1U_N8_GC_64
AF7
IO_L12N_T1U_N11_GC_64
AF5
IO_L12P_T1U_N10_GC_64
AE5
VCCO_64
AC5
VCCO_64
AD8
VCCO_64
AG7
IO_L13N_T2L_N1_GC_QBC_64
AD4
IO_L13P_T2L_N0_GC_QBC_64
AD5
IO_L14N_T2L_N3_GC_64
AC3
IO_L14P_T2L_N2_GC_64
AC4
IO_L15N_T2L_N5_AD11N_64
AB3
IO_L15P_T2L_N4_AD11P_64
AB4
IO_L16N_T2U_N7_QBC_AD3N_64
AD1
IO_L16P_T2U_N6_QBC_AD3P_64
AD2
IO_L17N_T2U_N9_AD10N_64
AC2
IO_L17P_T2U_N8_AD10P_64
AB2
IO_L18N_T2U_N11_AD2N_64
AC1
IO_L18P_T2U_N10_AD2P_64
AB1
IO_L19N_T3L_N1_DBC_AD9N_64
AH4
IO_L19P_T3L_N0_DBC_AD9P_64
AG4
IO_L20N_T3L_N3_AD1N_64
AH3
IO_L20P_T3L_N2_AD1P_64
AG3
IO_L21N_T3L_N5_AD8N_64
AF3
IO_L21P_T3L_N4_AD8P_64
AE3
IO_L22N_T3U_N7_DBC_AD0N_64
AF2
IO_L22P_T3U_N6_DBC_AD0P_64
AE2
IO_L23N_T3U_N9_64
AH1
IO_L23P_T3U_N8_64
AH2
IO_L24N_T3U_N11_64
AG1
IO_L24P_T3U_N10_64
AF1
VREF_64
AA7
C53
4.7uF
C52
470nF
R47
100R 1%
R46 240 1%