ASIX AX88772B USB 2.0 to Fast Ethernet Controller 数据手册

AX88772B

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"AX88772B_Datasheet_v107.pdf 是ASIX Electronics Corporation发布的一款USB2.0到10/100M快速以太网控制器的数据手册，该控制器型号为AX88772B，支持在线工具编程。" AX88772B是一款低功耗的USB2.0到10/100M快速以太网控制器，具有以下主要特点： 1. **单芯片集成**：AX88772B集成了USB2.0传输器和符合USB规范1.1及2.0的SIE（串行接口引擎），能够在单个芯片上实现USB2.0到10/100M快速以太网的转换。 2. **多种接口支持**：除了标准的10/100M快速以太网MAC/PHY外，还支持RMII（减少介质独立接口）和Reverse-RMII，能与HomePNA和HomePlug PHY配合工作，同时提供无胶合MAC-to-MAC连接。 3. **USB设备接口**：支持USB全速和高速模式，既可以由总线供电，也可以自供电。它还具备4或6个可编程端点，并且支持Auto Detach节能功能，当以太网电缆拔出时，自动断开与USB主机的连接。 4. **高性能数据传输**：通过专有的突发传输机制，AX88772B在USB总线上实现了高效率的数据包传输，这一技术已获得美国专利批准。 5. **快速以太网控制器**：集成了符合IEEE 802.3标准的10/100Mbps快速以太网MAC/PHY，兼容10BASE-T、100BASE-TX以及100BASE-FX，具备双绞线交叉检测和自动校正功能。 6. **节能特性**：设备支持多种节能模式，如Auto-Detach，有助于在不使用网络连接时降低功耗。 7. **物理层兼容性**：该控制器在物理层上与IEEE 802.3标准兼容，确保了在10BASE-T和100BASE-TX以太网标准下的正常工作，并且在光纤环境下也能兼容100BASE-FX。 AX88772B是一款设计精良、功能全面的USB2.0到以太网的接口控制器，适用于需要低功耗、高效率网络连接的嵌入式系统和移动设备。其丰富的接口选项和节能特性使其成为各种应用的理想选择，如智能家居设备、便携式媒体播放器、网络打印机等。用户可以利用其提供的在线工具进行编程，以适应特定的应用需求。

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AX88772BLF / AX88772BLI

Low-power

USB 2.0 to 10/100M Fast Ethernet Controller

 PIN configuration of MFA and MFB

Pin# 19

MFA2/RMII_N

Pin #21

MFA3/PHY_N

Description

1: MFB7~MFB0

0: RMII

1: MAC Mode

0: PHY Mode

Name

Function

Pin Type

MFB0

MFBIO0

Bidirection, controlled by MFBIOEN0

MFB1

MFBIO1

Bidirection, controlled by MFBIOEN1

MFB2

MFBIO2

Bidirection, controlled by MFBIOEN2

MFB3

MFBIO3

Bidirection, controlled by MFBIOEN3

MFB4

MFBIO4

Bidirection, controlled by MFBIOEN4

MFB5

MFBIO5

Bidirection, controlled by MFBIOEN5

MFB6

MFBIO6

Bidirection, controlled by MFBIOEN6

MFB7

MFBIO7

Bidirection, controlled by MFBIOEN7

MFA0

Refer to MFA

Configuration

MFA1

Refer to MFA

Configuration

MFA2

Refer to MFA

Configuration

MFA3

Refer to MFA

Configuration

MFB0

MFBIO0

Bidirection, controlled by MFBIOEN0

MFB1

CRSDV

Input

MFB2

TXEN

Output

MFB3

TXD1

Output

MFB4

TXD0

Output

MFB5

REF50

Input/Output control by EEPROM flag[1]

MFB6

RXD1

Input

MFB7

RXD0

Input

MFA0

MDC

Output

MFA1

MDIO

I/O

MFB0

MFBIO0

Bidirection, controlled by MFBIOEN0

MFB1

TXEN

Input

MFB2

CRSDV

Output

MFB3

RXD1

Output

MFB4

RXD0

Output

MFB5

REF50

Input/Output control by EEPROM flag[1]

MFB6

TXD1

Input

MFB7

TXD0

Input

MFA0

MDC

Input

MFA1

MDIO

I/O

AX88772BLF / AX88772BLI

Low-power

USB 2.0 to 10/100M Fast Ethernet Controller

3 Function Description

3.1 USB Core and Interface

The USB core and interface contains a USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol handshaking

block, USB standard command, vendor command registers, logic for supporting bulk transfer, and an interrupt transfer,

etc. The USB interface is used to communicate with a USB host controller and is compliant with USB specification V1.1

and V2.0.

3.2 10/100M Ethernet PHY

The 10/100M Fast Ethernet PHY is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal

oscillator, PLL-based clock multiplier, and a digital phase-locked loop for data/timing recovery. It provides

over-sampling mixed-signal transmit drivers compliant with 10/100BASE-TX transmit wave shaping / slew rate control

requirements. It has a robust mixed-signal loop adaptive equalizer for receiving signal recovery. It contains a baseline

wander corrective block to compensate data dependent offset due to AC coupling transformers. It supports

auto-negotiation and auto-MDIX functions.

3.3 MAC Core

The MAC core supports 802.3 and 802.3u MAC sub-layer functions, such as basic MAC frame receive and transmit, CRC

checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and handling in

half-duplex mode, etc. It provides a reduce-media-independent interface (RMII) for implementing Fast Ethernet and

HomePNA functions.

The MAC core interfaces to external RMII/Reverse-RMII interfaces and the embedded 10/100M Ethernet PHY. The

selection among the interfaces is done via setting Pin# 19 (MFA2/RMII_N) and Pin #21 (MFA3/PHY_N) of AX88772B

package pinout during power on reset (see 2.2) and using the USB vendor command, Software Interface Selection

core.

Figure 8 : Internal Data path Diagram of 10/100M Ethernet PHY and RMII/Reverse-RMII Interfaces

MAC

Core

10/100

Ethernet PHY

REFCLK, RXD [1:0], CRSDV,

TXD [1:0], TXEN

RXIP/RXIN

TXOP/TXON

RMII/Reverse

-RMII

AX88772BLF / AX88772BLI

Low-power

USB 2.0 to 10/100M Fast Ethernet Controller

3.4 Checksum Offload Engine (COE)

The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header

processing functions and real time checksum calculation in hardware

The COE supports the following features in layer 3:

 IP header parsing, including IPv4 and IPv6

 IPv6 routing header type 0 supported

 IPv6 in IPv4 tunnel supported

 IPv4 header checksum check and generation (There is no checksum field in IPv6 header)

 Version error detecting on RX direction for IP packets with version != 4 or 6

 Detecting on RX direction for IP packets with error header checksum

The COE supports the following features in layer 4:

 TCP and UDP checksum check and generation for non-fragmented packet

 ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet

 Packet filtering or checksum error indication on RX direction for TCP/UDP/ICMP/ICMPv6/IGMP packets

with error checksum

3.5 Operation Mode

For simple USB 2.0 to Ethernet applications, user can use the AX88772B, which operates with internal Ethernet PHY.

AX88772B supports following three operation modes: (Ref. 2.2 Hardware Setting For Operation Mode And

Multi-Function Pins)

1. MAC mode

2. PHY mode

Below provides a detailed description for the three operation modes:

 In MAC mode, the AX88772B Ethernet block is configured as an Ethernet MAC. From a system application

standpoint, AX88772B can be used as a USB 2.0 to LAN Adaptor (see Figure 2) or a USB 2.0 to Fast Ethernet and

HomePNA Combo (see Figure 3).

In MAC mode, the AX88772B internal datapath can work with internal Ethernet PHY or RMII interface by setting

Software Interface Selection register. Note that the PHY_ID for the internal Ethernet PHY and external one are

defined in below Table 3. Please refer to below Figure 9, Figure 10 for RMII example.

 In PHY mode, the AX88772B Ethernet block is configured as an Ethernet PHY interface. In this case, an external

microcontroller with Ethernet MAC can interface with AX88772B as if it were to interface with an Ethernet PHY

chip, and AX88772B can act as a USB to Reverse-RMII bridge chip for the microcontroller to provide USB 2.0

device interface for some system applications (see Figure 4).

Please refer to below Figure 11, Figure 12 for Reverse-RMII example.

STA PHY_ID

MAC mode

PHY mode

Embedded Ethernet PHY

PHY_ID [4:0]

10h

External Media Interface

PHY_ID [4:0]

{Secondary PHY_ID

[4:0]}

{Secondary PHY_ID [4:1], 0}

Note: The value of Secondary PHY_ID [4:0] is defined in EEPROM memory map 4.1.6

Table 3 : PHY_ID Definition Source

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