AD9681：8通道14位125 MSPS低功耗高速串行LVDS ADC手册

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AD9681是一款高性能的8通道、14位、125兆样本每秒（MSPS）串行低电压差分信号（SerialLVDS）模拟到数字转换器（ADC）。这款产品专为对功耗敏感且需要高数据速率和精度的大型医疗设备设计，如生物医学信号采集系统、成像设备或者高级生理监护设备。该ADC的主要特点包括： 1. **低功耗**：AD9681设计时注重能效，每通道在125 MSPS下仅消耗110毫瓦的功率，同时支持可扩展的电源选项，使得在满足高性能需求的同时实现能源的有效管理。 2. **集成度高**：8个独立的ADC通道集成在一个单一的封装内，节省了电路板空间，有利于系统紧凑设计。 3. **高采样率与信号质量**：14位分辨率确保了高精度的数据转换，信噪比（SNR）达到74分贝满量程（FS），而信道间杂讯抑制比（SFDR）高达90分贝共模抑制比（c.o.m.d.B.），表现出优秀的噪声和干扰抑制能力。 4. **线性性能**：典型值下的失调（DNL）为±0.8LSB（Least Significant Bit，最低有效位），积分非线性（INL）为±1.2LSB，这些指标反映了转换过程中的精确度和一致性。 5. **串行接口**：采用ANSI-644标准的SerialLVDS接口，简化了系统设计，降低了线路复杂性，并允许长距离传输数据。 6. **低功耗模式**：提供一个低功耗、减小信号选项，类似于IEEE 1596.3标准，适用于那些对功耗敏感的应用场合。 7. **文档支持**：文档详尽，由Analog Devices公司提供，包括修订C版本的数据表，确保用户可以获取到最新的技术信息和建议。 8. **版权与商标**：所有内容受版权保护，以及Analog Devices公司的商标和注册商标权所有，体现了其作为业界领导者在知识产权方面的严谨态度。 AD9681是一款能满足医疗设备高精度、高速度和低功耗需求的理想选择，是工程师在设计多通道、高性能生物医学信号采集系统时值得考虑的关键组件。在应用时，务必注意遵守文档中的责任声明和专利注意事项，以避免潜在的法律问题。

Data Sheet AD9681

Rev. C | Page 7 of 40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, A

= −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

Symbol Temp Min Typ Max Unit

CLOCK

Input Clock Rate Full 10 1000 MHz

Conversion Rate

Full 10 125 MSPS

Clock Pulse Width High t

Full 4.00 ns

Clock Pulse Width Low t

Full 4.00 ns

OUTPUT PARAMETERS

Propagation Delay t

Full 1.5 2.3 3.1 ns

Rise Time (20% to 80%) t

Full 300 ps

Fall Time (20% to 80%) t

Full 300 ps

FCO±1, FCO±2 Propagation Delay t

FCO

Full 1.5 2.3 3.1 ns

DCO±1, DCO±2 Propagation Delay

CPD

Full t

FCO

+ (t

SAMPLE

/16) ns

DCO±1, DCO±2 to Data Delay

DATA

Full (t

SAMPLE

/16) − 300 (t

SAMPLE

/16) (t

SAMPLE

/16) + 300 ps

DCO±1, DCO±2 to FCO±1, FCO±2 Delay

FRAME

Full (t

SAMPLE

/16) − 300 (t

SAMPLE

/16) (t

SAMPLE

/16) + 300 ps

Lane Delay t

90 ps

Data to Data Skew t

DATA-MAX

− t

DATA-MIN

Full ±50 ±200 ps

Wake-Up Time (Standby) 25°C 250 ns

Wake-Up Time (Power-Down)

25°C 375 μs

Pipeline Latency Full 16

Clock

cycles

APERTURE

Aperture Delay t

25°C 1 ns

Aperture Uncertainty (Jitter) t

25°C 135 fs rms

Out-of-Range Recovery Time 25°C 1

Clock

cycles

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

Measured on standard FR-4 material.

Adjustable using the SPI. The conversion rate is the clock rate after the divider.

The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode.

SAMPLE

/16 is based on the number of bits in two LVDS data lanes. t

SAMPLE

= 1/f

SAMPLE

Wake-up time is defined as the time required to return to normal operation from power-down mode.

AD9681 Data Sheet

Rev. C | Page 8 of 40

TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit Unit

SYNC TIMING REQUIREMENTS

SSYNC

SYNC to rising edge of CLK+ setup time 1.2 ns min

HSYNC

SYNC to rising edge of CLK+ hold time −0.2 ns min

SPI TIMING REQUIREMENTS See Figure 53

Setup time between the data and the rising edge of SCLK 2 ns min

Hold time between the data and the rising edge of SCLK 2 ns min

CLK

Period of the SCLK 40 ns min

Setup time between CSB1/CSB2 and SCLK 2 ns min

Hold time between CSB1/CSB2 and SCLK 2 ns min

HIGH

SCLK pulse width high 10 ns min

LOW

SCLK pulse width low 10 ns min

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the

SCLK falling edge (not shown in Figure 53)

10 ns min

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative to the

SCLK rising edge (not shown in Figure 53)

10 ns min

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Table 21 for SPI register setting of output modes.

D0–A1

D0+A1

D1–A1

D1+A1

FCO–1, FCO–2

BYTEWISE

MODE

FCO+1, FCO+2

D0–A1

D0+A1

D1–A1

D1+A1

FCO–1, FCO–2

DCO–1, DCO–2

DCO+1, DCO+2

CLK+

VIN±x1, VIN±x2

CLK–

DCO–1, DCO–2

FCO+1, FCO+2

BITWISE

MODE

SDR

DDR

MSB

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

MSB

N – 16

D12

N – 16

D11

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

MSB

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

MSB

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D12

N – 17

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D12

N – 16

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

DATA

FCO

FRAME

CPD

N – 1

N + 1

11537-003

Figure 3. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

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