Copyright © 2009-2011 Future Technology Devices International Limited 3
Document Reference No.: FT000183
Interfacing FTDI USB Hi-Speed Devices to a JTAG TAP Application Note AN_129
Version 1.1
Clearance No.: FTDI# 114
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Select-IR-Scan
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Update-IR
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test-logic-resetTest-Logic-Reset
Run-Test-Idle Select-DR-Scan
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update-drUpdate-DR
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JTAG TAP State Machine
Transitions on state of TMS on positive edge of TCK
Figure 1.1 – IEEE 1149.1 (JTAG) state machine
The boundary scan circuitry is accessed through a Test Access Port (TAP) controller with four dedicated
and mandatory I/O signals: Test Clock (TCK) - the input clock for the state machine, Test Mode Select
(TMS) - the input used to navigate through the state machine, Test Data In (TDI) - the input containing
serial data or instructions and Test Data Out (TDO) - the output containing serial data or instructions. An
optional fifth signal, Test Reset (TRST#) can be implemented on a TAP. TRST# is an asynchronous reset
that forces the state machine immediately to the Test-Logic-Reset state. It is important to note that
even without TRST#, the state machine can always be forced to Test-Logic-Reset from any other state by
holding TMS high for a maximum of five clock cycles.
TMS
TCK
TDO
TDI
TDI TDI
TMS TMS
TCK TCK
TDO TDO
Figure 1.2 – IEEE 1149.1 (JTAG) TAP chain
As shown in Figure 1.2, devices in a JTAG chain share TCK and TMS. This forces all devices on a single
chain to be in the same state within the state machine. The JTAG master controller connects its data
output to TDI. Each device in the chain connects its TDI to the previous TDO. Finally, the last device in
the chain connects its TDO to the controllers data input. Other connection schemes are possible;
however, they are beyond the scope of this application note.
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