PCI9054技术手册：I/O加速器与数据管道架构解析

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"PCI9054db-1C.pdf" 本文档是关于PCI9054寄存器的手册，提供了该芯片的初步信息。虽然尽力确保信息准确，但可能存在误导或错误的陈述，因为文档与实际芯片开发并行编写，可能会有所变更。这个描述旨在作为一个活文档，在PCI 9054设计过程中不断更新，为读者提供广泛的PCI 9054技术概述。 PCI9054是PLX Technology公司的一款产品，是一款I/O加速器，采用了数据管道（DataPipe）架构技术。这种技术包含两个DMA（直接存储器访问）通道，能够提高数据传输效率和系统性能。作为PCI（外围组件互连）接口的发起者，PCI9054可以作为主机控制器与PCI总线上的其他设备通信。 1.1. PCI9054 I/O Accelerator PCI9054设计用于提升系统的输入/输出性能，特别是在处理高速数据流时。它通过优化I/O操作，减少了CPU对这些任务的干预，从而释放CPU资源执行其他更重要的计算任务。 1.2. 数据管道（DataPipe）架构技术 1.2.1 双DMA通道数据管道架构的核心是其双DMA通道设计，允许同时进行读取和写入操作，显著提高了数据传输速率和吞吐量。每个DMA通道都可以独立工作，处理不同的数据流，增强了系统的并发处理能力。此外，文档还提到PLX Technology保留随时更改产品的权利，而无需事先通知，这表明实际产品可能与当前文档描述存在细微差异，即所谓的“errata”。用户在使用PCI9054时应关注最新的技术更新和修订。对于那些需要技术支持的用户，PLX Technology提供了多种联系方式，包括网址、电子邮件地址、电话和传真。这份数据手册的版本为1.0，发布于1998年11月，表明这是早期的资料，可能后续有更新版本。 PCI9054是一种高性能的I/O加速器，利用创新的数据管道架构和双DMA通道设计，提高了PCI总线的性能和效率。了解这些核心特点对于理解和使用PCI9054芯片进行系统设计至关重要。

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PLX Technology, Inc., 1998 Page xvi Version 1.0

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List of Figures PCI 9054 Data Book

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PLX Technology, Inc., 1998 Page xvii Version 1.0

LIST OF FIGURES

Typical Adapter Block Diagram ...........................................................................................................................................................1

PCI 9054 Internal Block Diagram ........................................................................................................................................................2

Figure 1-1. High-Performance MPC850 or MPC860 PowerQUICC Adapter Design ..............................................................................3

Figure 1-2. High-Performance CompactPCI Adapter............................................................................................................................5

Figure 1-3. High-Performance Embedded Adapter...............................................................................................................................5

Figure 2-1. Wait States .....................................................................................................................................................................18

Figure 2-2. Big/Little Endian—32-Bit Local Bus..................................................................................................................................22

Figure 2-3. Big/Little Endian—16-Bit Local Bus..................................................................................................................................22

Figure 2-4. Big/Little Endian—8-Bit Local Bus....................................................................................................................................23

Figure 2-5. Serial EEPROM Memory Map .........................................................................................................................................27

Figure 2-6. PCI 9054 Internal Register Access ..................................................................................................................................28

Figure 2-7. Address Decode Mode....................................................................................................................................................28

Figure 3-1. Direct Master Access of the PCI Bus ...............................................................................................................................37

Figure 3-2. Direct Master Write .........................................................................................................................................................38

Figure 3-3. Direct Master Read .........................................................................................................................................................38

Figure 3-4. Dual Address Timing.......................................................................................................................................................41

Figure 3-5. Direct Slave PCI v2.1 Delayed Reads..............................................................................................................................43

Figure 3-6. Direct Slave PCI 9054 Read Ahead Mode........................................................................................................................43

Figure 3-7. Direct Slave Write ...........................................................................................................................................................44

Figure 3-8. Direct Slave Read...........................................................................................................................................................44

Figure 3-9. Direct Slave Access of the Local Bus...............................................................................................................................46

Figure 3-10. Block DMA Mode Initialization (Single Address or Dual Address PCI) .............................................................................51

Figure 3-11. DMA, PCI-to-Local Bus .................................................................................................................................................51

Figure 3-12. DMA, Local-to-PCI Bus .................................................................................................................................................52

Figure 3-13. Dual Address Timing.....................................................................................................................................................52

Figure 3-14. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus)...................................................53

Figure 3-15. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus).....................................................53

Figure 3-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address

(DMADAC0, DMADAC1) Register Dependent]..............................................................................................................56

Figure 3-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address

(DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent] .........................................................................................56

Figure 3-18. Local-to-PCI Bus DMA Data Transfer Operation.............................................................................................................57

Figure 3-19. PCI-to-Local Bus DMA Data Transfer Operation.............................................................................................................57

Figure 4-1. Wait States ...................................................................................................................................................................107

Figure 4-2. Big/Little Endian—32-Bit Local Bus................................................................................................................................110

Figure 4-3. Big/Little Endian—16-Bit Local Bus................................................................................................................................110

Figure 4-4. Big/Little Endian—8-Bit Local Bus..................................................................................................................................111

Figure 4-5. Serial EEPROM Memory Map .......................................................................................................................................115

Figure 4-6. PCI 9054 Internal Register Access ................................................................................................................................116

List of Figures PCI 9054 Data Book

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PLX Technology, Inc., 1998 Page xviii Version 1.0

Figure 4-7. Address Decode Mode..................................................................................................................................................116

Figure 5-1. Direct Master Access of the PCI Bus .............................................................................................................................125

Figure 5-2. Direct Master Write .......................................................................................................................................................126

Figure 5-3. Direct Master Read .......................................................................................................................................................126

Figure 5-4. Dual Address Timing.....................................................................................................................................................129

Figure 5-5. Direct Slave PCI v2.1 Delayed Reads............................................................................................................................130

Figure 5-6. Direct Slave PCI 9054 Read Ahead Mode......................................................................................................................131

Figure 5-7. Direct Slave Write .........................................................................................................................................................131

Figure 5-8. Direct Slave Read.........................................................................................................................................................131

Figure 5-9. Direct Slave Access of the Local Bus.............................................................................................................................133

Figure 5-10. Block DMA Mode Initialization (Single Address or Dual Address PCI) ...........................................................................138

Figure 5-11. DMA, PCI-to-Local Bus ...............................................................................................................................................138

Figure 5-12. DMA, Local-to-PCI Bus ...............................................................................................................................................139

Figure 5-13. Dual Address Timing...................................................................................................................................................139

Figure 5-14. Scatter/Gather DMA Mode from PCI-to-Local Bus (Control Access from the Local Bus).................................................140

Figure 5-15. Scatter/Gather DMA Mode from Local-to-PCI Bus (Control Access from the PCI Bus)...................................................140

Figure 5-16. Scatter/Gather DMA Mode Descriptor Initialization [PCI SAC/DAC PCI Address

(DMADAC0, DMADAC1) Register Dependent]............................................................................................................141

Figure 5-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address

(DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent] .......................................................................................141

Figure 5-18. Local-to-PCI Bus DMA Data Transfer Operation...........................................................................................................143

Figure 5-19. PCI-to-Local Bus DMA Data Transfer Operation...........................................................................................................143

Figure 6-1. Mailbox and Doorbell Message Passing.........................................................................................................................205

Figure 6-2. Interrupt and Error Sources ...........................................................................................................................................206

Figure 7-1. Typical I

O Server/Adapter Card Design ........................................................................................................................211

Figure 7-2. Driver Architecture Compared........................................................................................................................................211

Figure 7-3. Circular FIFO Operation ................................................................................................................................................214

Figure 9-1. Redirection of BD_SEL#................................................................................................................................................220

Figure 9-2. Board Healthy...............................................................................................................................................................220

Figure 9-3. PCI Reset .....................................................................................................................................................................220

Figure 9-4. Hot Swap Capabilities Register Bit Definition .................................................................................................................222

Figure 10-1. VPD Capabilities Register ...........................................................................................................................................223

Figure 13-1. PCI 9054 Local Input Setup and Hold Waveform..........................................................................................................293

Figure 13-2. PCI 9054 Local Output Delay ......................................................................................................................................295

Figure 13-3. PCI 9054 ALE Output Delay to the Local Clock............................................................................................................296

Figure 14-1. 176-Pin PQFP Package Mechanical Dimensions .........................................................................................................297

Figure 14-2. 176-Pin PQFP PCI 9054 Pinout...................................................................................................................................298

Figure 14-3. 225-Pin PBGA Package Mechanical Dimensions .........................................................................................................299

Figure 14-4. 225-Pin PBGA Package Layout (Underside View)........................................................................................................300

List of Tables PCI 9054 Data Book

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PLX Technology, Inc., 1998 Page xix Version 1.0

LIST OF TABLES

Table 1-1. FIFO Depth........................................................................................................................................................................5

Table 1-2. Programmable Local Bus Modes ........................................................................................................................................6

Table 1-3. PCI 9054 Data Assignment Convention ..............................................................................................................................7

Table 1-4. Comparison of PCI 9054, PCI 9080, and PCI 9050 .............................................................................................................8

Table 1-5. PCI 9054 PCI Signal Listing (M, C, or J Modes) ..................................................................................................................9

Table 1-6. PCI 9054 Local Signal Listing (M, C, or J Modes)..............................................................................................................10

Table 2-1. PCI Target Command Codes............................................................................................................................................17

Table 2-2. DMA Master Command Codes .........................................................................................................................................17

Table 2-3. Local-to-PCI Memory Access............................................................................................................................................17

Table 2-4. Local-to-PCI I/O Access ...................................................................................................................................................17

Table 2-5. Local-to-PCI Configuration Access....................................................................................................................................17

Table 2-6. Local Bus Types (176-Pin PQFP) .....................................................................................................................................18

Table 2-7. Local Bus Types (225-Pin PBGA) .....................................................................................................................................18

Table 2-8. Burst and Bterm on the Local Bus.....................................................................................................................................19

Table 2-9. Burst-4 Lword Mode.........................................................................................................................................................19

Table 2-10. PCI Bus Little Endian Byte Lanes....................................................................................................................................20

Table 2-11. Byte Number and Lane Cross-Reference........................................................................................................................21

Table 2-12. Big/Little Endian Program Mode......................................................................................................................................21

Table 2-13. Cycles Reference Tables................................................................................................................................................21

Table 2-14. Upper Lword Lane Transfer ............................................................................................................................................22

Table 2-15. Upper Word Lane Transfer .............................................................................................................................................22

Table 2-16. Lower Word Lane Transfer .............................................................................................................................................22

Table 2-17. Upper Byte Lane Transfer...............................................................................................................................................22

Table 2-18. Lower Byte Lane Transfer...............................................................................................................................................22

Table 2-19. Serial EEPROM Guidelines ............................................................................................................................................24

Table 2-20. Long Serial EEPROM Load Registers.............................................................................................................................25

Table 2-21. Extra Long Serial EEPROM Load Registers....................................................................................................................26

Table 2-22. New Capabilities Function Support Features...................................................................................................................27

Table 3-1. Response to FIFO Full or Empty.......................................................................................................................................36

Table 3-2. Direct Slave Burst Mode Cycle Detection..........................................................................................................................44

Table 3-3. Data Bus TSIZ[0:1] Contents for Write Cycles ...................................................................................................................47

Table 3-4. Data Bus TSIZ[0:1] Requirements for Read Cycles ...........................................................................................................47

Table 3-5. DMA................................................................................................................................................................................52

Table 3-6. Normal DMA with EOT Function .......................................................................................................................................52

Table 3-7. Demand Mode DMA, Channel 0 .......................................................................................................................................58

Table 3-8. Any DMA Transfer Channel 0/1 with EOT Functionality .....................................................................................................59

Table 4-1. PCI Target Command Codes..........................................................................................................................................105

Table 4-2. DMA Master Command Codes .......................................................................................................................................105

List of Tables PCI 9054 Data Book

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PLX Technology, Inc., 1998 Page xx Version 1.0

Table 4-3. Local-to-PCI Memory Access..........................................................................................................................................105

Table 4-4. Local-to-PCI I/O Access .................................................................................................................................................105

Table 4-5. Local-to-PCI Configuration Access..................................................................................................................................105

Table 4-6. Local Bus Types (176-Pin PQFP) ...................................................................................................................................106

Table 4-7. Local Bus Types (225-Pin PBGA) ...................................................................................................................................106

Table 4-8. Burst and Bterm on the Local Bus...................................................................................................................................107

Table 4-9. Burst-4 Lword Mode.......................................................................................................................................................108

Table 4-10. PCI Bus Little Endian Byte Lanes..................................................................................................................................109

Table 4-11. Byte Number and Lane Cross-Reference......................................................................................................................109

Table 4-12. Big/Little Endian Program Mode....................................................................................................................................109

Table 4-13. Cycles Reference Tables..............................................................................................................................................109

Table 4-14. Upper Lword Lane Transfer ..........................................................................................................................................110

Table 4-15. Upper Word Lane Transfer ...........................................................................................................................................110

Table 4-16. Lower Word Lane Transfer ...........................................................................................................................................110

Table 4-17. Upper Byte Lane Transfer.............................................................................................................................................110

Table 4-18. Lower Byte Lane Transfer.............................................................................................................................................110

Table 4-19. Serial EEPROM Guidelines ..........................................................................................................................................112

Table 4-20. Long Serial EEPROM Load Registers...........................................................................................................................113

Table 4-21. Extra Long Serial EEPROM Load Registers..................................................................................................................114

Table 4-22. New Capabilities Function Support Features.................................................................................................................115

Table 5-1. Response to FIFO Full or Empty.....................................................................................................................................124

Table 5-2. DMA Local Burst Mode...................................................................................................................................................139

Table 7-1. Queue Starting Address .................................................................................................................................................212

Table 7-2. Circular FIFO Summary..................................................................................................................................................216

Table 9-1. Hot Swap Control...........................................................................................................................................................222

Table 11-1. New Registers Definitions Summary (As Compared to the PCI 9080).............................................................................225

Table 11-2. PCI Configuration Registers..........................................................................................................................................226

Table 11-3. Local Configuration Registers .......................................................................................................................................227

Table 11-4. Runtime Registers........................................................................................................................................................228

Table 11-5. DMA Registers.............................................................................................................................................................229

Table 11-6. Messaging Queue Registers.........................................................................................................................................230

Table 11-7. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ..........................................................................................231

Table 11-8. (PCICR; PCI:04h, LOC:04h) PCI Command Register ....................................................................................................231

Table 11-9. (PCISR; PCI:06h, LOC:06h) PCI Status Register ..........................................................................................................232

Table 11-10. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register...............................................................................................232

Table 11-11. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register ...................................................................................233

Table 11-12. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register....................................................................................233

Table 11-13. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Bus Latency Timer Register...................................................................................233

Table 11-14. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register............................................................................................233

Table 11-15. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register.........................................................................234

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