AT32AP7001高性能低功耗微控制器数据手册

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"AT32AP7001英文数据手册" AT32AP7001是一款高性能、低功耗的AVR®32位微控制器，由Atmel公司设计。这款微控制器在150MHz的工作频率下可以实现210DMIPS（每秒百万指令）的吞吐量，展现了强大的处理能力。其内部集成了16KB的指令缓存和16KB的数据缓存，优化了内存访问速度，提升了系统的响应效率。该微控制器包含一个内存管理单元（MMU），使得它能够支持操作系统（如Linux、FreeRTOS等）的运行。采用单周期RISC指令集，包括SIMD（单指令多数据）和DSP（数字信号处理）指令，提高了计算密集型任务的处理速度。此外，硬件加速的Java功能进一步增强了其在嵌入式应用中的性能。 AT32AP7001内建了一个像素协处理器，专为视频加速而设计，能够执行色彩空间转换（如YUV到RGB）、图像缩放和滤波以及四分之一像素运动补偿等功能，这对于高清视频处理和实时图像处理至关重要。在总线系统方面，AT32AP7001采用多层总线结构，通过独立的数据总线实现高效率的数据传输，提升了系统性能。它拥有32KB的SRAM作为内部数据存储器，满足快速存取需求。外部存储接口是该微控制器的一大亮点，支持SDRAM、DataFlash、SRAM、MMC、SD卡、CompactFlash、SmartMedia、NAND Flash等多种类型的外部存储设备，提供了丰富的扩展性。直接内存访问控制器（DMA）允许在CPU不介入的情况下访问外部存储，减少了CPU负担，提高了系统整体效率。中断控制器具有单独可屏蔽的中断功能，每个中断请求都有可编程的优先级和自动向量地址，确保了中断处理的灵活性和实时性。系统功能还包括电源和时钟管理器，内置晶体振荡器带有锁相环（PLL）以提供精确的时钟源；看门狗定时器用于系统稳定性和故障检测；实时时钟（RTC）则用于时间相关的应用；以及6个多功能计数器/定时器，满足不同应用场景的需求。总而言之，AT32AP7001是一款综合性能强大、功能全面的32位微控制器，适合于需要高效能、低功耗、多媒体处理和复杂系统集成的应用，如工业控制、汽车电子、消费电子等领域。

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32015G–AVR32–09/09

AT32AP7001

7. AVR32 AP CPU

Rev.: 1.0.0.0

This chapter gives an overview of the AVR32 AP CPU. AVR32 AP is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, caches and MMU is

presented. For further details, see the AVR32 Architecture Manual and the AVR32 AP Technical

Reference Manual.

7.1 AVR32 Architecture

AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-

sensitive embedded applications, with particular emphasis on low power consumption and high

code density. In addition, the instruction set architecture has been tuned to allow a variety of

microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance

processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been com-

piled and analyzed to achieve the best code density in its class. In addition to lowering the

memory requirements, a compact code size also contributes to the core’s low power characteris-

tics. The processor supports byte and half-word data types without penalty in code size and

performance.

Memory load and store operations are provided for byte, half-word, word and double word data

with automatic sign- or zero extension of half-word and byte data.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

single cycle. Load and store instructions have several different formats in order to reduce code

size and speed up execution.

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the

Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values

from function calls and is used implicitly by some instructions.

7.2 The AVR32 AP CPU

AVR32 AP targets high-performance applications, and provides an advanced OCD system, effi-

cient data and instruction caches, and a full MMU. Figure 7-1 on page 17 displays the contents

of AVR32 AP.

32015G–AVR32–09/09

AT32AP7001

7.2.5 Caches and write buffer

AVR32 AP implements 16K data and 16K instruction caches. The caches are 4-way set asso-

ciative. Each cache has a 32-bit System Bus master interface connecting it to the bus. The

instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64-

bit interface to the load-store pipeline. The caches use a least recently used allocate-on-read-

miss replacement policy. The caches are virtually tagged, physically indexed, avoiding the need

to flush them on task switch.

The caches provide locking on a per-line basis, allowing code and data to be permanently

locked in the caches for timing-critical code. The data cache also allows prefetching of data

using the pref instruction.

Accesses to the instruction and data caches are tagged as cacheable or uncacheable on a per-

page basis by the MMU. Data cache writes are tagged as write-through or writeback on a per-

page basis by the MMU.

The data cache has a 32-byte combining write buffer, to avoid stalling the CPU when writing to

external memory. Writes are tagged as bufferable or unbufferable on a per-page basis by the

MMU. Bufferable writes to sequential addresses are placed in the buffer, allowing for example a

sequence of byte writes from the CPU to be combined into word transfers on the bus. A sync

instruction is provided to explicitly flush the write buffer.

7.2.6 Unaligned reference handling

AVR32 AP has hardware support for performing unaligned memory accesses. This will reduce

the memory footprint needed by some applications, as well as speed up other applications oper-

ating on unaligned data.

AVR32 AP is able to perform certain word-sized load and store instructions of any alignment,

and word-aligned st.d and ld.d. Any other unaligned memory access will cause an MMU address

exception. All coprocessor memory access instructions require word-aligned pointers. Double-

word-sized accesses with word-aligned pointers will automatically be performed as two word-

sized accesses.

The following table shows the instructions with support for unaligned addresses. All other

instructions require aligned addresses. Accessing an unaligned address may require several

clock cycles, refer to the AVR32 AP Technical Reference Manual for details.

Table 7-1. Instructions with unaligned reference support

Instruction Supported alignment

ld.w Any

st.w Any

lddsp Any

lddpc Any

stdsp Any

ld.d Word

st.d Word

All coprocessor memory access instruction Word

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