82C59A CMOS中断控制器：高速、兼容与低功耗
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82C59A是一款高性能的CMOS优先级中断控制器，由Harris公司制造，采用先进的2微米CMOS工艺。这款集成电路（IC）旨在简化多级优先级系统中对系统中央处理器（CPU）的依赖，通过提供高速和工业标准配置，使得它能够与多种微处理器兼容，如80C286、80286、80C86/88、8086/88以及8080等。它的主要特点包括：
1. **工作频率选择**：82C59A提供三个版本，包括12.5MHz、8MHz和5MHz，分别对应不同的性能等级。12.5MHz版本支持无等待状态操作，适合与80C286和8MHz的80C86/88配合。
2. **兼容性**：该芯片针脚与NMOS 8259A兼容，这意味着可以轻松替换现有的8259A硬件，同时保持与多种Intel微处理器的兼容性。
3. **优先级控制**：82C59A是八级优先级控制器，可以通过编程扩展至64级，以处理复杂优先级场景。
4. **中断模式设置**：具有可编程中断模式，允许根据应用需求定制中断行为。
5. **功能扩展**：支持个体请求屏蔽功能，允许独立控制每个中断源。
6. **设计特点**：采用全静态设计，确保了低功耗运行，最大静态电流ICCSB为10μA，而ICCOP在1MHz时的最大电流为1mA。
7. **电源需求**：单个5V电源供电，满足低电压应用的需求。
8. **温度范围**：不同版本有不同的工作温度范围：
- C82C59A：0°C至+70°C
- I82C59A-40°C至+85°C
- M82C59A：-55°C至+125°C
综上，82C59A芯片是一种高效能的中断管理解决方案，适用于对中断处理有高效率和灵活性要求的系统，尤其在需要兼容多种微处理器且需要处理复杂优先级级别的应用场景中表现出色。其设计精良，功耗低，温度范围广泛，适应各种环境和应用条件。
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A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that sys-
tem throughput would drastically increase, and thus, more
tasks could be assumed by the microcomputer to further
enhance its cost effectiveness.
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which
of the incoming requests is of the highest importance (prior-
ity), ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific func-
tional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine associ-
ated with the requesting device. This “pointer” is an address
in a vectoring table and will often be referred to, in this docu-
ment, as vectoring data.
82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for expand-
ability to other 82C59As (up to 64 levels). It is programmed
by system software as an I/O peripheral. A selection of prior-
ity modes is available to the programmer so that the manner
in which the requests are processed by the 82C59A can be
configured to match system requirements. The priority
modes can be changed or reconfigured dynamically at any
time during main program operation. This means that the
complete interrupt structure can be defined as required,
based on the total system environment.
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the inter-
rupt levels which are requesting service, and the ISR is used to
store all the interrupt levels which are currently being serviced.
ROM
I/O (2)
RAM
CPU
INT
I/O (1)
I/O (N)
PIC
FIGURE 3. INTERRUPT METHOD
IR0
IR1
IR2
CASCADE
BUFFER
COMPARATOR
READ/
WRITE
LOGIC
DATA
BUS
BUFFER
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT MASK REG
(IMR)
INTERRUPT
REQUEST
REG
(IRR)
CONTROL LOGIC
INT
INTA
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
RD
WR
A
0
SP/EN
CS
D
7
- D
0
INTERNAL BUS
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
82C59A
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