HyperBus技术详解：高性能DDR总线的信号优化

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"HyperBus时序规范：低信号计数，高性能DDR总线" HyperBus（Hyper Bus Specification）是一种高速、低引脚数的接口技术，主要用于连接主机系统（如微处理器、微控制器或ASIC设备）与存储器（如RAM、Flash存储器）和其他外围设备。该规范设计的主要目标是实现高性能数据传输，同时降低信号数量，从而减少电路板空间占用，简化系统设计，并降低功耗。 HyperBus接口采用DDR（Double Data Rate）技术，这意味着数据在时钟的上升沿和下降沿都被传输，显著提高了数据传输速率。相比于传统的SPI、I2C或UART等接口，HyperBus具有更高的带宽和更低的延迟，适用于需要快速读写操作的应用场景。主要特性包括： 1. **低信号计数**：HyperBus接口通常只需要8条信号线（4个数据线、2个时钟线、1个片选线和1个命令/地址线），大大减少了所需的物理连接，使得硬件设计更为简洁。 2. **高性能**：由于使用DDR技术，数据传输速率可达到几百兆比特每秒，甚至吉比特每秒级别，满足高速存储访问的需求。 3. **通用的主-从总线架构**：HyperBus支持多设备连接，主机可以控制多个从设备，方便构建复杂的系统架构。 4. **灵活性**：HyperBus协议允许不同类型的存储器和设备共存，适应性强，能广泛应用于各种嵌入式系统。 5. **低功耗**：通过优化的协议和时序设计，HyperBus能够在保持高性能的同时，减少能源消耗，适合电池供电的便携式设备。 6. **易于集成**：由于其简单的接口和协议，HyperBus容易被系统设计师集成到现有设计中，缩短产品开发周期。 7. **兼容性**：尽管由Cypress Semiconductor（现为Infineon Technologies的一部分）开发，但HyperBus规范已被广泛接受，其他厂商也提供兼容的解决方案，确保了市场的广泛支持和长期可用性。在具体应用中，例如在物联网（IoT）设备、汽车电子、工业控制、移动设备等领域，HyperBus因其高效率和低功耗而受到青睐。Infineon将继续提供和支持HyperBus产品，确保文档内容和订购零件编号的连续性。总体来说，HyperBus时序规范是现代电子设计中提高性能、降低成本和复杂性的理想选择，尤其对于那些需要快速数据交换和低功耗特性的系统。

Document Number: 001-99253 Rev. *H Page 7 of 44

HyperBus™ Specification

HyperBus Specification

2. HyperBus Signal Descriptions

2.1 Input/Output Summary

HyperBus has a mandatory set of signals as well as optional signals that are supported by some but not all HyperBus compatible

devices. Active Low signal names have a hash symbol (#) suffix.

Table 2.1 Mandatory I/O Summary

Symbol Type Description

CS#

Master Output, Slave

Input

Chip Select. Bus transactions are initiated with a High to Low transition. Bus transactions are terminated with a

Low to High transition. The master device has a separate CS# for each slave.

CK,

CK#

Master Output, Slave

Input

Differential Clock. Command, address, and data information is output with respect to the crossing of the CK and

CK# signals. Differential clock is used on 1.8V I/O devices.

Single Ended Clock. CK# is not used on 3.0V devices, only a single ended CK is used.

The clock is not required to be free-running.

DQ[7:0] Input/Output

Data Input/Output. Command, Address, and Data information is transferred on these signals during Read and

Write transactions.

RWDS Input/Output

Read Write Data Strobe. During the Command/Address portion of all bus transactions RWDS is a slave output

and indicates whether additional initial latency is required. Slave output during read data transfer, data is edge

aligned with R WDS. Slave input during data transfer in write transactions to function as a data mask.

(High = additional latency, Low = no additional latency).

Table 2.2 Optional I/O Summary

Symbol Type Description

RESET

Master Output, Slave

Input,

Internal Pull-up

Hardware RESET. When Low the slave device will self initialize and return to the Standby state. RWDS and

DQ[7:0] are placed into the High-Z state when RESET# is Low. The slave RESET# input includes a weak pull-

up, if RESET# is left unconnected it will be pulled up to the High state.

RSTO#

Master Input, Slave

Output, Open Drain

RESET Output. RSTO# is an open-drain output used to indicate when a Power-On-Reset (POR) is occurring

within the slave device and can be used as a system reset signal. Upon completion of the internal POR, a user

defined timeout period can extend the RSTO# Low time. Following the POR and user defined extension time,

RSTO# signal will cease driving Low so the master or external resistance can pull the signal to High . There is no

internal pull-up required on this signal, however, some slave devices may provide an internal pull-up as a device

specific feature.

INT#

Master Input, Slave

Output, Open Drain

Interrupt Output. When INT# is Low the slave device is indicating that an internal event has occurred. This

signal is intended to be used as a system interrupt from the slave device to indicate that an on-chip event has

occurred. INT# is an open-drain output. There is no internal pull-up required on this signal, however, some slave

devices may provide an internal pull-up as a device specific feature.

Document Number: 001-99253 Rev. *H Page 8 of 44

HyperBus™ Specification

3. HyperBus Protocol

All bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low with clock in idle state

(CK=Low and CK#=High). The first three clock cycles transfer three words of Command/Address (CA0, CA1, CA2) information to

define the transaction characteristics. The Command/Address words are presented with DDR timing, using the first six clock edges.

The following characteristics are defined by the Command/Address information:

 Read or Write transaction.

 Address Space: memory array space or register space.

– Register space is used to access Device Identification (ID) registers and Configuration Registers (CR) that identify the

device characteristics and determine the slave specific behavior of read and write transfers on the HyperBus interface.

 Whether a transaction will use a linear or wrapped burst sequence.

 The target row (and half-page) address (upper order address).

 The target column (word within half-page) address (lower order address).

During the Command/Address (CA) portion of all transactions, RWDS is used by the memory to indicate whether additional initial

access latency will be inserted.

Following the Command/Address information, a number of clock cycles without data transfer may be used to satisfy any initial

latency requirements before data is transferred. The number of clock cycles inserted is defined by a slave configuration register

(latency count) value. If RWDS was High during the CA period an additional latency count is inserted.

Some slave devices may require write transactions with zero latency between the CA cycles and following write data transfers.

Writes with zero initial latency, do not have a turn-around period for RWDS. The slave device will always drive RWDS during the

Command-Address period to indicate whether extended latency is required for a transaction that has initial latency. However, the

RWDS is driven before the slave device has received the first byte of CA, that is, before the slave knows whether the transaction is

a read or write, to memory space or register space. In the case of a write with zero latency, the RWDS state during the CA period

does not affect the initial latency of zero. Since master write data immediately follows the Command-Address period in this case, the

slave may continue to drive RWDS Low or may take RWDS to High-Z during write data transfer. The master must not drive RWDS

during Writes with zero latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are

written (full word writes). Writes without initial latency are generally used for register space writes but the requirement for writes with

zero latency is slave device dependent. Writes with zero latency may be required for memory space or register space or neither,

depending on the slave device capability.

When data transfer begins, read data is edge aligned with RWDS transitions or write data is center aligned with single-ended clock

edges or differential clock CK/CK# crossings. During read data transfer, RWDS serves as a source synchronous read data timing

strobe. During write data transfer, clock edges or crossings provide the data timing reference and RWDS is used as a data mask.

When RWDS is low during a write data transfer, the data byte is written into memory; if RWDS is high during the transfer the byte is

not written.

Data is always transferred as 16-bit values with the first eight bits (byte A) transferred on a High going CK (write data) or following a

RWDS rising edge (read data) and the second eight bits (byte B) is transferred on the Low going CK edge or following the falling

RWDS edge.

After the target data has been transferred, the host completes the transaction by driving CS# High with clock idle. Data transfers can

be ended at any time by bringing CS# High when clock is idle.

The clock is not required to be free-running. The clock may be idle while CS# is High or may stop in the idle state while CS# is Low

(this is called Active Clock Stop). Support for Active Clock Stop is slave device dependent. It is an optional HyperBus device feature.

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