I2C总线规格与用户手册 Rev. 7.0 - 2021年10月

需积分: 5 10 浏览量更新于2024-06-22 收藏 724KB PDF 举报

"I2C-bus specification and user manual Rev. 7.0 - 1 October 2021" 本文档是I2C总线规格和用户手册的第七版，由Philips Semiconductors（现为NXPSemiconductors）编写，详细介绍了I2C（Inter-Integrated Circuit）总线协议及其应用。I2C总线是一种用于设备间高效通信的双向两线制接口，只需两条线路：串行数据线（SDA）和串行时钟线（SCL）。它支持串行、8位定向的双向数据传输。该规范涵盖了I2C总线的不同工作模式，包括： 1. 标准模式（Standard-mode）：数据传输速率可达100kbit/s。 2. 快速模式（Fast-mode）：数据传输速率提升至400kbit/s。 3. 快速模式Plus（Fast-mode Plus, Fm+）：数据传输速率进一步提高到1Mbit/s。 4. 高速模式（High-speed mode）：在该模式下，速率可达到3.4Mbit/s。 5. 超快速模式（UltraFast-mode）：这是一种单向模式，数据传输速率高达5Mbit/s。手册中可能包含了关于如何设计和实现I2C兼容设备的详细信息，包括信号电平、时序要求、数据包格式、错误检测机制以及总线仲裁等关键概念。此外，文档还提到了对术语的更新，例如将"主/从"（master/slave）替换为"控制器/目标"（controller/target），以符合MIPI I3C规范和NXP的包容性语言项目。自上一版本以来，手册进行了以下修改： - 更新了表格5，可能涉及了I2C总线的电气特性或时序参数。 - 在整份文档中统一了术语，用"控制器/目标"取代了"主/从"。 - 新增了第9节，这部分可能包含新的功能、应用场景或故障排查指南。对于硬件工程师、嵌入式系统开发者以及需要理解和使用I2C总线的人员来说，这份用户手册是非常宝贵的参考资料。它详细阐述了I2C总线的各个方面，帮助开发者正确地集成和优化I2C通信，以实现不同电子设备间的高效协同工作。

NXP Semiconductors

UM10204

C-bus specification and user manual

CLK

SCL

counter

reset

wait

state

start counting

HIGH period

mbc632

Figure 7. Clock synchronization during the arbitration procedure

When all controllers concerned have counted off their LOW period, the clock line is

released and goes HIGH. There is then no difference between the controller clocks and

the state of the SCL line, and all the controllers start counting their HIGH periods. The

first controller to complete its HIGH period pulls the SCL line LOW again.

In this way, a synchronized SCL clock is generated with its LOW period determined by

the controller with the longest clock LOW period, and its HIGH period determined by the

one with the shortest clock HIGH period.

3.1.8 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more

than one controller is used in the system. Targets are not involved in the arbitration

procedure. A controller may start a transfer only if the bus is free. Two controllers may

generate a START condition within the minimum hold time (t

HD;STA

) of the START

condition which results in a valid START condition on the bus. Arbitration is then required

to determine which controller will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each controller

checks to see if the SDA level matches what it has sent. This process may take many

bits. Two controllers can actually complete an entire transaction without error, as long

as the transmissions are identical. The first time a controller tries to send a HIGH, but

detects that the SDA level is LOW, the controller knows that it has lost the arbitration and

turns off its SDA output driver. The other controller goes on to complete its transaction.

No information is lost during the arbitration process. A controller that loses the arbitration

can generate clock pulses until the end of the byte in which it loses the arbitration and

must restart its transaction when the bus is free.

If a controller also incorporates a target function and it loses arbitration during the

addressing stage, it is possible that the winning controller is trying to address it. The

losing controller must therefore switch over immediately to its target mode.

Figure 8 shows the arbitration procedure for two controllers. More may be involved

depending on how many controllers are connected to the bus. The moment there is a

difference between the internal data level of the controller generating DATA1 and the

actual level on the SDA line, the DATA1 output is switched off. This does not affect the

data transfer initiated by the winning controller.

User manual Rev. 7.0 — 1 October 2021

11 / 62

NXP Semiconductors

UM10204

C-bus specification and user manual

msc609

DATA 1

DATA 2

SDA

SCL

controller 1 loses arbitration

DATA 1 SDA

Figure 8. Arbitration procedure of two controllers

Since control of the I

C-bus is decided solely on the address and data sent by competing

controllers, there is no central controller, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the

moment when one controller sends a repeated START or a STOP condition while the

other controller is still sending data. In other words, the following combinations result in

an undefined condition:

• Controller 1 sends a repeated START condition and controller 2 sends a data bit.

• Controller 1 sends a STOP condition and controller 2 sends a data bit.

• Controller 1 sends a repeated START condition and controller 2 sends a STOP

condition.

3.1.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction

cannot continue until the line is released HIGH again. Clock stretching is optional and in

fact, most target devices do not include an SCL driver so they are unable to stretch the

clock.

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs

more time to store a received byte or prepare another byte to be transmitted. Targets can

then hold the SCL line LOW after reception and acknowledgment of a byte to force the

controller into a wait state until the target is ready for the next byte transfer in a type of

handshake procedure (see Figure 7).

On the bit level, a device such as a microcontroller with or without limited hardware for

the I

C-bus, can slow down the bus clock by extending each clock LOW period. The

speed of any controller is adapted to the internal operating rate of this device.

In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2).

3.1.10 The target address and R/W bit

Data transfers follow the format shown in Figure 9. After the START condition (S), a

target address is sent. This address is seven bits long followed by an eighth bit which is

a data direction bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates

a request for data (READ) (refer to Figure 10). A data transfer is always terminated by

User manual Rev. 7.0 — 1 October 2021

12 / 62

NXP Semiconductors

UM10204

C-bus specification and user manual

a STOP condition (P) generated by the controller. However, if a controller still wishes to

communicate on the bus, it can generate a repeated START condition (Sr) and address

another target without first generating a STOP condition. Various combinations of read/

write formats are then possible within such a transfer.

1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STOP

condition

START

condition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

mbc604

Figure 9. A complete data transfer

mbc608

R/W

LSBMSB

target address

Figure 10. The first byte after the START procedure

Possible data transfer formats are:

• Controller-transmitter transmits to target-receiver. The transfer direction is not changed

(see Figure 11). The target receiver acknowledges each byte.

• Controller reads target immediately after first byte (see Figure 12). At the moment of

the first acknowledge, the controller-transmitter becomes a controller-receiver and the

target-receiver becomes a target-transmitter. This first acknowledge is still generated

by the target. The controller generates subsequent acknowledges. The STOP condition

is generated by the controller, which sends a not-acknowledge (A) just before the

STOP condition.

• Combined format (see Figure 13). During a change of direction within a transfer,

the START condition and the target address are both repeated, but with the R/W bit

reversed. If a controller-receiver sends a repeated START condition, it sends a not-

acknowledge (A) just before the repeated START condition.

Notes:

1. Combined formats can be used, for example, to control a serial memory. The internal

memory location must be written during the first data byte. After the START condition

and target address is repeated, data can be transferred.

2. All decisions on auto-increment or decrement of previously accessed memory

locations, etc., are taken by the designer of the device.

3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in

the sequence.

4. I

C-bus compatible devices must reset their bus logic on receipt of a START or

repeated START condition such that they all anticipate the sending of a target

User manual Rev. 7.0 — 1 October 2021

13 / 62

剩余61页未读，继续阅读

似水轻愁

粉丝: 2
资源: 5

I2C总线规格与用户手册 Rev. 7.0 - 2021年10月

最新资源