MT9T111开发指南：1/4英寸3.1MP SOC CMOS数字图像传感器

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"MT9T111 Developer Guide 是Aptina Imaging Corporation针对1/4英寸3.1百万像素（3.1Mp）系统级芯片（SOC）CMOS数字图像传感器MT9T111编写的开发指南。此文档旨在为硬件和软件工程师提供开发基于Aptina MT9T111 CMOS数字图像传感器的相机系统的参考。传感器集成了一系列高级的片上相机功能，并通过串行接口进行编程。" MT9T111是Aptina公司推出的一款先进的CMOS图像传感器，设计用于移动电话等应用中。其主要特点包括： 1. **系统级芯片（SOC）设计**：MT9T111将图像传感器、信号处理和控制逻辑集成在一个芯片上，减少了外部组件的需求，降低了系统复杂性和成本。 2. **高分辨率**：这款传感器提供310万像素的分辨率，符合1/4英寸的光学格式，适合高质量图像和视频捕捉。 3. **片上功能**：MT9T111集成了复杂的图像处理功能，如自动曝光、自动白平衡和色彩校正，有助于优化图像质量。 4. **串行接口**：传感器可通过串行接口进行编程，允许用户根据应用需求调整设置，增强了灵活性和定制性。 5. **评估和参考**：文档明确指出，产品和规格可能会发生变化，而提供的信息适用于评估和参考目的，实际产品的性能应以Aptina的生产数据表为准。 6. **更新与支持**：开发者可以通过访问Aptina的官方网站获取最新的数据表和技术支持，确保使用的数据是最新的。 7. **保修声明**：Aptina仅保证产品满足其生产数据表规格，具体的产品保修政策应遵循Aptina的条款。该开发指南涵盖了以下内容： - **硬件接口**：详细介绍了与MT9T111连接的物理接口，包括电源、I/O引脚、数据传输协议等。 - **相机控制**：阐述如何通过软件控制传感器的各种参数，如曝光时间、增益控制、帧率等。 - **寄存器编程**：提供了关于如何配置和操作传感器内部寄存器的指导，以实现特定功能或优化性能。 - **应用示例**：可能包含针对不同应用场景的实例，帮助开发者理解如何在实际项目中应用MT9T111。 - **故障排查**：可能包括常见问题和解决方法，以帮助开发者在遇到问题时快速找到解决方案。 MT9T111 Developer Guide是一份全面的技术文档，对于那些想要利用MT9T111开发高性能、小巧便携的相机系统的工程师来说，是一份不可或缺的参考资料。

PDF: 4749051511/Source:7788125767 Aptina reserves the right to change products or specifications without notice.

MT9T111_DG - Rev. B 9/10 EN

MT9T111: Developer Guide

I/O Signals

Preliminary

I/O Signals

The MT9T111 has digital I/O signals like a typical CMOS circuit.

•I/O voltage (V

DD_IO) is separate from core voltages (VDD and VDD_PLL) and analog

voltages (V

AA and VAA_PIX).

• If an input signal is not used, it must be tied to HIGH (V

DD_IO) or LOW (DGND).

• Input signals with internal pull-up or pull-down resistors can be left floating (see

Table 3 for details).

• If an output signal is not used, leave it floating.

• If a bidirectional signal is not used, it must be either configured as an output, or if

configured as an input, it must be tied to either HIGH or LOW.

• Never exceed the absolute maximum electrical specification (refer to the electrical

specifications section of the MT9T111 data sheet).

In general, when V

DD_IO is on, all the input signals must be driven by the host, while the

output signals are driven by the sensor. The MT9T111 implements a fail-safe I/O for all

I/O signals to prevent I/O failure when V

DD_IO is not applied.

If some of the features are not used in the sensor, the input signals must be connected to

either HIGH or LOW, as shown in Table 3.

Table 3: Attributes of I/O and Power Supply Signals

Signal Name Type Supply Reference

Fail–

Safe

I/O If Unused Slew Rate

Hysteresis

Input

Internal

Pull-Up/

Down

EXTCLK Input V

DD_IO/DGND Yes N/A N/A Yes No

RESET_BAR Input V

DD_IO/DGND Yes N/A N/A N/A Yes (PU)

SADDR Input VDD_IO/DGND Yes N/A N/A N/A No

SCLK Input V

DD_IO/DGND Yes N/A N/A Yes No

STANDBY Input V

DD_IO/DGND Yes DGND N/A N/A No

RX_DN Input VDDIO_RX/

GNDIO_RX

N/A No connection N/A N/A No

RX_DP Input V

DDIO_RX/

GNDIO_RX

N/A No connection N/A N/A No

RX_CN Input V

DDIO_RX/

GNDIO_RX

N/A No connection N/A N/A No

RX_CP Input V

DDIO_RX/

GNDIO_RX

N/A No connection N/A N/A No

GPIO[3:0] I/O V

DD_IO/DGND Yes DGND or VDD_IO R0x001E[6:4] N/A No

DATA

I/O VDD_IO/DGND Yes N/A N/A Yes No

DATA_2

I/O VDD_IO/DGND N/A No connection N/A N/A No

VGPIO[7:0] I/O VDD_VGPIO/

GND_VGPIO

N/A No connection N/A N/A No

OUT[7:0] Output VDD_IO/DGND Yes No connection R0x001E[2:0] N/A No

FRAME_VALID Output V

DD_IO/DGND Yes No connection R0x001E[2:0] N/A No

LINE_VALID Output V

DD_IO/DGND Yes No connection R0x001E[2:0] N/A No

PIXCLK Output V

DD_IO/DGND Yes No connection R0x001E[10:8] N/A No

DOUT_P Output VDDIO_TX/

GNDIO_TX

N/A No connection N/A N/A No

DOUT_N Output V

DDIO_TX/

GNDIO_TX

N/A No connection N/A N/A No

PDF: 4749051511/Source:7788125767 Aptina reserves the right to change products or specifications without notice.

MT9T111_DG - Rev. B 9/10 EN

MT9T111: Developer Guide

I/O Signals

Preliminary

Low-Noise Operation

For low-noise operation, the MT9T111 requires separate power supplies for analog and

digital. Incoming digital and analog ground conductors need to be separated in the

imager module. Both power supply rails should be decoupled from ground, using capac-

itors located as close as possible to the die. The use of inductance filters is not recom-

mended on the power supplies or output signals.

The MT9T111 also supports different digital core, MIPI, and I/O power domains, as

shown in Table 5. The PLL and analog domains require clean power sources.

Notes: 1. DGND and GND_IO are tied together to meet ESD standards.

2. AGND and DGND are all isolated internally.

If there are five pins available for system power connections, Aptina recommends the

connections, as shown in Table 6.

If there are only four pins available for system power connections, Aptina recommends

the connections, as shown in Table 7.

Table 5: Power Supply Descriptions

Voltage Name Description Voltage Ground Reference Note

DD Digital logic 1.8V DGND 1, 2

DD_IO Input/output 1.8V or 2.8V GND_IO 1, 2

VPP OTP memory 8.5V DGND –

DD_PLL PLL 2.8V DGND 2

DDIO_Tx MIPI TX 1.8V GNDIO_TX –

VDDIO_RX MIPI RX 1.8V GNDIO_RX –

DDIO_VGPIO VGPIO 2.8V GNDIO_VPGIO –

AA Analog circuitry 2.8V AGND 2

VAA_PIX Pixel array 2.8V AGND 2

Table 6: Recommended System Power Connections (5 pins)

Pin Number Power/Ground Type Voltage Power Supply Signals

1 Digital power 1.8V V

DD,VDDIO_TX, VDDIO_RX

2 Digital power 1.8V or 2.8V V

DD_IO, VDDIO_VGPIO

3Analogpower2.8V V

AA,VAA_PIX,VDD_PLL

GND

DGND, GND_IO, GNDIO_TX, GNDIO_RX, GNDIO_VGPIO

GND AGND

Table 7: Recommended System Power Connections (4 pins)

Pin Number Power Type Voltage Power Supply Signals

1 Digital power 1.8V V

DD,VDD_IO, VDDIO_TX, VDDIO_RX, VDDIO_VGPIO

2 Analog power 2.8V VAA,VAA_PIX,VDD_PLL

GND DGND, GND_IO, GNDIO_TX, GNDIO_RX, GNDIO_VGPIO

GND AGND

PDF: 4749051511/Source:7788125767 Aptina reserves the right to change products or specifications without notice.

MT9T111_DG - Rev. B 9/10 EN

MT9T111: Developer Guide

PLL and Clock Divider

Preliminary

PLL and Clock Divider

The MT9T111 requires a single input clock source (EXTCLK) to operate. EXTCLK is used

as the reference clock to the PLL, which generates all the internal clocks. The sensor

provides three output clocks (PIXCLK, external sensor CLK, and MIPI CLK). PIXCLK is

used for the parallel output data bus, whereas the MIPICLK is used for the serial MIPI

output. The MT9T111 also provides the clock for an external sensor to be used in dual

camera applications.

The PLL can accept an input clock with a frequency between 6 and 54 MHz. A PLL circuit

in the MT9T111 synthesizes an arbitrary clock frequency to be used as the time base

within the device. It allows flexible system design where the clock supplied to the device

through EXTCLK may be higher or lower than the desired PIXCLK output frequency.

On power-up, the PLL is bypassed and the MT9T111 initially runs off of the EXTCLK.

When the PLL is enabled, the MT9T111 uses the PLL output (VCO) clock to generate all

the internal clocks. All of the clocks shown in Figure 5 on page 22 are derived from the

VCO (see Table 10 on page 23). Table 9 on page 22 shows how to calculate the internal

clock frequencies.

The PLL divider registers must be programmed before the PLL is enabled. Aptina recom-

mends using the MT9T111’s Register Wizard (part of DevWare), a frame rate and timing

calculating tool, to generate the register values. The user only needs to specify input

clock frequency (EXTCLK), desired output clock frequency (PIXCLK), and frame rate

requirements.

The sensor clock will be calculated based on frame rate requirements. Based on sensor

clock frequency and the required pixel clock, the SOC clock frequency is calculated. The

SOC clock frequency should be as low as possible to provide the lowest power consump-

tion, but still maintain continuous data flow from sensor to the output interface. A RX

FIFO and a TX FIFO with programmable watermarks allows for the continuous flow of

image data.

For programming the external sensor clock, refer to “Master Two-WireSerial Interface

and External Sensor Control Interface” on page 37.

For more detailed programming of the sensor core clock with frame rate calculation,

refer to the MT9T013 1/4-Inch 3.1Mp CMOS digital image sensor data sheet.

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