MT9M112开发指南：1.3MP SOC CMOS数码影像传感器详解

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"MT9M112 Developer Guide 是一份针对 Micron Technology, Inc. 生产的 1/4 英寸 1.3 兆像素 System-on-Chip (SOC) CMOS 数字图像传感器的专业开发指南。该文档旨在为硬件和软件工程师提供帮助，设计和优化使用 MT9M112 在移动电话应用中无缝集成的相机系统。MT9M112集成了先进的芯片内摄像头功能，并通过串行接口进行编程，提供了关于硬件接口、相机控制以及寄存器编程建议，以确保最佳的图像质量。文档的主要内容包括： 1. 产品概述：MT9M112 是一个完整的 SOC 图像传感器，特别适合于紧凑型设计和移动设备的高分辨率成像需求。其 1.3 兆像素的分辨率确保了丰富的细节捕捉能力。 2. 适用范围：这份指南专门针对 MT9M112型号，因此在使用时需确保与所讨论的组件兼容。 3. 文档目的：作为开发者指南，它详细解释了如何利用传感器的内置特性，如ISP（图像信号处理器）、自动曝光、白平衡等，以及如何通过串行接口进行高级功能配置。 4. 硬件接口：指南中会涵盖传感器与主处理器、内存以及其他外围设备之间的物理连接方式，以及相应的引脚定义和电气规范。 5. 相机控制：介绍如何通过控制寄存器来调整镜头控制、快门速度、ISO感光度等相机设置，以适应不同的应用场景和环境条件。 6. 编程推荐：提供了最佳实践和代码示例，帮助工程师理解和实施传感器的编程模式，确保稳定性和性能。 7. 版权信息：文档由 Micron Technology, Inc. 创作，所有权利保留，可能随着产品的更新而有所变动，建议访问公司网站获取最新规格。 8. 标准和约定：文档中可能会用到特定的符号、缩写和术语，以便于理解和遵循标准开发流程和安全规定。 MT9M112 Developer Guide 是一个全面的工具，它不仅涵盖了硬件设计者需要了解的硬件接口和功能配置，还为软件工程师提供了关键的编程指导，旨在协助用户充分发挥这款图像传感器的潜力，实现高质量的视觉解决方案。"

MT9M112: Developer Guide

Hardware Design and Operating Modes

PDF: 09005aef81e8b850/Source: 09005aef81e8ba81 Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9M112_DG_3.fm - Rev. B 6/07 EN

Micron Confidential and Proprietary

Figure 4: Operating Mode Diagram for MT9M112

Notes: 1. There are implied transitions from each mode back to complete shutdown whenever all

power supplies are turned off.

2. There are implied transitions from each mode back to power on whenever any power sup-

ply is turned off.

3. In reset, all power supplies have reached their final saturation value and RESET# is driven

LOW. This initializes the sensor to a known state and all default register values are loaded.

(RESET# = 0)

AND (VDD_DIS = 0)

(VDD_DIS = 1)

(R0x00D[3:2] = 0b10) AND (STANDBY = 0)

(VDD_DIS = 0) AND

(R0x00D[3:2] = 0b01)

OR (STANDBY = 1)

CLKIN <10 cycles

Post

Standby

(CLKIN = 0) OR

(CLKIN <74 cycles)

CLKIN <80 cycles

(i.e., 1 row time)

Pre

Standby

CLKIN <5 cycles

Pre

Disable

CLKIN AND (VDD_DIS = 1) AND

(R0x00D[3:2] = 0

b00)

AND (STANDBY = 1)

(R0x00D[3:2] = 0b01) OR (STANDBY = 1)

CLKIN AND (VDD_DIS = 0)

AND (R0x00D[3:2] = 0b10)

AND (STANDBY = 0)

(VDD_DIS = 0) AND

(RESET# = 1)

(CLKIN is ON) AND (CLKIN 74 cycles) AND RESET# = 1)

CLKIN 74 cycles

CLKIN 10 cycles

CLKIN 80 cycles

(VDD = 0) AND (VDDPLL = 0) AND (VAA = 0)

AND (VAAPIX = 0) AND (V

DDQ = 0)

(CLKIN is OFF) OR

(CLKIN <74 cycles)

OR (RESET# = 0)

(VDD = 1) OR (VDDPLL = 1) OR (VAA = 1)

OR (VAAPIX = 1) OR (V

DDQ = 1)

DD = 0) OR (VDDPLL = 0) OR (VAA = 0)

OR (VAAPIX = 0) OR (V

DDQ = 0)

(VDD = 1) AND (VDDPLL = 1) AND (VAA = 1) AND

(VAAPIX = 1) AND (V

DDQ = 1) AND (RESET# = 0)

Power

Reset

Active

(CLKIN 5 cycles)

AND (VDD_DIS = 1)

Complete

Shutdown

VDD

Disable

Standby

Post

Disable

PDF: 09005aef81e8b850/Source: 09005aef81e8ba81 Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9M112_DG_3.fm - Rev. B 6/07 EN

MT9M112: Developer Guide

Hardware Design and Operating Modes

Micron Confidential and Proprietary

Power-Up Sequences

There are two power-up sequences:

1. Initial power-up of all supplies including V

DDQ.

2. Power-up of core digital V

DD following VDD disable mode.

Initial Power-Up

During initial power-up, always assert RESET# = 0. This is called power-on reset (POR);

it refers to the combination of the transitional states, power on and reset, between the

complete shutdown and active modes, as shown in Figure 4 on page 11. All output

signals are driven LOW if STANDBY = 0 and are High-Z if STANDBY = 1. The device is

not in low-power mode while RESET# = 0 during initial power-up, regardless of the state

of the standby signal. VDD_DIS must not be asserted during initial power-up. See “I/O

Signals” on page 20 and “PLL and Clocks” on page 26 for more details.

There are no constraints concerning the order in which the various power supplies are

applied to the part. As long as a hardware reset is asserted following the stabilization of

supplies, the part will be properly initialized. However, to minimize power consump-

tion, all power supplies must be simultaneously applied with no more than 1ms of skew.

A hardware reset (RESET# = 0) is required following initial power-up.

Post VDD_DIS Power-Up

The power-up sequence following VDD_DIS is similar to initial power-up. Memory,

flip-flops, and register states are lost when VDD_DIS is asserted. When VDD_DIS is

de-asserted, the internal logic state is unknown.

External hardware reset (RESET# = 0) is optional following post V

DD disable power-up.

See “Vdd Disable” on page 8 for more details.

The part is not in a low-power state immediately following de-assertion of VDD_DIS,

regardless of standby status.

Reset Sequences

CMOS logic requires a reset to operate reliably after power-up; this requirement applies

to the MT9M112 as well. Because there is no power-on reset circuit, a hardware reset

(RESET# = 0) is required during initial power-up. Because the two-wire serial interface

logic must initialize after power-up, software reset may not be substituted for hardware

reset.

Once the sensor is properly initialized and running, the MT9M112 may be reset in hard-

ware by driving RESET# LOW, or through software by writing to a register through the

two-wire serial interface. The internal state of the MT9M112 following reset is identical

whether the device is reset by hardware or software.

All output signals are defined during initial power-up with RESET# = 0 without CLKIN

being active. For a proper reset sequence for the rest of the sensor, assert RESET# = 0

during initial power-up for at least 1µs after all power supplies have stabilized and

CLKIN is active (being clocked). Driving RESET# = 0 does not put the part in a low-power

state.

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