Xilinx Zynq系列芯片数据手册：多种型号与规格概述

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本文档是关于Xilinx Zynq系列FPGA（Field-Programmable Gate Array）产品的数据手册，DS187版本为v1.21，发布日期为2020年12月1日。Zynq-7000 SoC（System-on-Chip）系列包括多个型号，如XC7Z100-2FFG900I、XC7Z045-1FFG676C等，这些器件提供不同性能等级(-3, -2, -1, -1L)，其中-1L等级特别强调低功耗设计，允许在PL（Programmable Logic）VCCINT/VCCBRAM电压上工作，可以选择0.95V或1.0V，以降低静态和动态功耗。 Zynq系列的特点在于集成处理系统（PS，Processing System），即包含RISC-V架构的CPU核心，以及可编程逻辑部分（PL）。产品规格涵盖了广泛的性能指标，如速度等级、供电选项、功耗特性，以及针对商业、扩展、工业和扩展（Q-temp）温度范围内的DC和AC操作特性。这些SoC适用于多种应用，如嵌入式系统、实时控制、数字信号处理等，支持高性能计算和低功耗设计需求。在选择设备时，用户需要考虑其性能需求、功耗预算、以及工作环境的温度条件。例如，XCZU4EV-1SFVC784和XCZU5EV-2SFVC784可能是针对特定应用设计的，而XCZU9EG-2FFVB1156I则可能具有更高级别的性能或更大的集成度。此外，文档还提及了Xilinx品牌的商标权益，以及与Arm、AMBA、Cortex等技术的关系，这些都表明Zynq-7000系列采用了Arm架构和知识产权，以及AMBA标准接口，确保了与其他兼容硬件的高效协同工作。这份数据手册为设计者提供了全面的Zynq-7000系列FPGA产品信息，以便他们根据项目需求选择合适的器件，并了解其在不同工作条件下的行为和性能表现。对于从事Xilinx平台设计或寻求深入了解该系列产品的工程师来说，这是不可或缺的参考资料。

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)

DS187 (v1.21) December 1, 2020 www.xilinx.com

Product Specification 12

LVDS DC Specifications (LVDS_25)

Table 12: Complementary Differential SelectIO DC Input and Output Levels

I/O Standard

ICM

(1)

(2)

(3)

(4)

V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min

DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 V

CCO

–0.400 8.00 –8.00

DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 V

CCO

–0.400 8.00 –8.00

DIFF_HSTL_II 0.300 0.750 1.125 0.100 – 0.400 V

CCO

–0.400 16.00 –16.00

DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 – 0.400 V

CCO

–0.400 16.00 –16.00

DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% V

CCO

80% V

CCO

0.100 –0.100

DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 – 10% V

CCO

90% V

CCO

0.100 –0.100

DIFF_SSTL135 0.300 0.675 1.000 0.100 – (V

CCO

/2) – 0.150 (V

CCO

/2) + 0.150 13.0 –13.0

DIFF_SSTL135_R 0.300 0.675 1.000 0.100 – (V

CCO

/2) – 0.150 (V

CCO

/2) + 0.150 8.9 –8.9

DIFF_SSTL15 0.300 0.750 1.125 0.100 – (V

CCO

/2) – 0.175 (V

CCO

/2) + 0.175 13.0 –13.0

DIFF_SSTL15_R 0.300 0.750 1.125 0.100 – (V

CCO

/2) – 0.175 (V

CCO

/2) + 0.175 8.9 –8.9

DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (V

CCO

/2) – 0.470 (V

CCO

/2) + 0.470 8.00 –8.00

DIFF_SSTL18_II 0.300 0.900 1.425 0.100 – (V

CCO

/2) – 0.600 (V

CCO

/2) + 0.600 13.4 –13.4

Notes:

1. V

ICM

is the input common mode voltage.

2. V

is the input differential voltage (Q–Q).

3. V

is the single-ended low-output voltage.

4. V

is the single-ended high-output voltage.

Table 13: LVDS_25 DC Specifications

(1)

Symbol DC Parameter Conditions Min Typ Max Units

CCO

Supply voltage 2.375 2.5 2.625 V

Output High voltage for Q and Q R

= 100 across Q and Q signals – – 1.675 V

Output Low voltage for Q and Q R

= 100 across Q and Q signals 0.700 – – V

ODIFF

Differential output voltage:

(Q – Q

), Q = High

–Q), Q=High

= 100 across Q and Q signals 247 350 600 mV

OCM

Output common-mode voltage R

= 100 across Q and Q signals 1.00 1.25 1.425 V

IDIFF

Differential input voltage:

(Q – Q

), Q = High

–Q), Q=High

100 350 600 mV

ICM

Input common-mode voltage 0.3 1.2 1.500 V

Notes:

1. Differential inputs for LVDS_25 can be placed in banks with V

CCO

levels that are different from the required level for outputs. Consult the

7 Series FPGAs SelectIO Resources User Guide (UG471

) for more information.

Send Feedback

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)

DS187 (v1.21) December 1, 2020 www.xilinx.com

Product Specification 13

AC Switching Characteristics

All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and

Vivado® Design Suite 2016.3 as outlined in Table 14.

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or

Production. Each designation is defined as follows:

Advance Product Specification

These specifications are based on simulations only and are typically available soon after device design specifications are

frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting

might still occur.

Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with

this designation are intended to give a better indication of the expected performance of production silicon. The probability

of under-reporting delays is greatly reduced as compared to Advance data.

Production Product Specification

These specifications are released once enough production silicon of a particular device family member has been

characterized to provide full correlation between specifications and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest

speed grades transition to Production before faster speed grades.

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are

representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and

back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another depends

completely on the status of the fabrication process for each device. Ta b l e 1 5 correlates the current status of each Zynq-7000

device on a per speed grade basis.

Table 14: Zynq-7000 SoC Speed Specification Version By Device

ISE 14.7 Vivado 2016.3 Device

1.08 1.11 XC7Z010 and XC7Z020

N/A 1.11 XC7Z007S, XC7Z012S, XC7Z014S, and XC7Z015

1.06 1.09 XA7Z010

and XA7Z020

1.06 1.10 XQ7Z020

Table 15: Zynq-7000 Device Speed Grade Designations

Device

Speed Grade Designations

Advance Preliminary Production

XC7Z007S -2E, -2I, -1C, -1I

XC7Z012S -2E, -2I, -1C, -1I

XC7Z014S -2E, -2I, -1C, -1I

XC7Z010 -3E, -2E, -2I, -1C, -1I, -1LI

XC7Z015 -3E, -2E, -2I, -1C, -1I, -1LI

Send Feedback

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)

DS187 (v1.21) December 1, 2020 www.xilinx.com

Product Specification 14

Production Silicon and Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is

released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent

speed specification releases.

Table 16 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed

specification version and software revisions. The software and speed specifications listed are the minimum releases required

for production. All subsequent releases of software and speed specifications are valid.

Selecting the Correct Speed Grade and Voltage in the Vivado Tools

It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.

To select the -3, -2, or -1 (PL 1.0V) speed specifications in the Vivado tools, select the Zynq-7000, XA Zynq-7000, or

Defense Grade Zynq-7000 sub-family, and then select the part name that is the device name followed by the package name

followed by the speed grade. For example, select the xc7z020clg484-3 part name for the XC7Z020 device in the CLG484

package and -3 speed grade.

XC7Z020 -3E, -2E, -2I, -1C, -1I, -1LI

XA7Z010 -1I, -1Q

XA7Z020 -1I, -1Q

XQ7Z020 -2I, -1I, -1Q, -1LI

Table 16: Zynq-7000 Device Production Software and Speed Specification Release

Device

Speed Grade Designations

-3E -2E -2I -1C -1I -1LI -1Q

XC7Z007S N/A Vivado tools 2016.3 v1.11 N/A N/A

XC7Z012S N/A Vivado tools 2016.3 v1.11 N/A N/A

XC7Z014S N/A Vivado tools 2016.3 v1.11 N/A N/A

XC7Z010 ISE tools 14.5

v1.06 and

Vivado tools 2013.1

v1.06

ISE tools 14.4 and the 14.4 device pack v1.05

and Vivado tools 2013.1 v1.06

Vivado tools

2014.4 v1.11

N/A

XC7Z015

Vivado tools 2013.4 v1.09

Vivado tools

2014.4 v1.11

N/A

XC7Z020 ISE tools 14.5

v1.06 and

Vivado tools 2013.1

v1.06

ISE tools 14.4 and the 14.4 device pack v1.05

and Vivado tools 2013.1 v1.06

Vivado tools

2014.4 v1.11

N/A

XA7Z010

N/A

ISE tools 14.5

v1.04 and

Vivado tools 2013.1

v1.04

N/A

ISE tools 14.6

v1.05 and

Vivado tools 2013.2

v1.05

XA7Z020

N/A

ISE tools 14.5

v1.04 and

Vivado tools 2013.1

v1.04

N/A

ISE tools 14.6

v1.05 and

Vivado tools 2013.2

v1.05

XQ7Z020

N/A

ISE tools 14.6

v1.05 and

Vivado tools 2013.2

v1.05

N/A

ISE tools 14.6

v1.05 and

Vivado tools 2013.2

v1.05

Vivado tools

2015.4 v1.10

ISE tools 14.7

v1.06 and

Vivado tools 2013.3

v1.06

Table 15: Zynq-7000 Device Speed Grade Designations (Cont’d)

Device

Speed Grade Designations

Advance Preliminary Production

Send Feedback

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)

DS187 (v1.21) December 1, 2020 www.xilinx.com

Product Specification 15

To select the -1LI (PL 0.95V) speed specifications in the Vivado tools, select the Zynq-7000 sub-family and then select the

part name that is the device name followed by an i followed by the package name followed by the speed grade. For example,

select the xc7z020iclg484-1L part name for the XC7Z020 device in the CLG484 package and -1LI (PL 0.95V) speed grade.

The -1LI (PL 0.95V) speed specifications are not supported in the ISE tools.

A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See

Table 16 for the subset of the Zynq-7000 devices supported in the ISE tools.

PS Performance Characteristics

For further design requirement details, refer to the Zynq-7000 SoC Technical Reference Manual (UG585).

Table 17: CPU Clock Domains Performance

Symbol Clock Ratio Description

Speed Grade

Units

-3 -2 -1C/-1I/-1LI -1Q

CPU_6X4X_621_MAX

(1)

6:2:1

Maximum CPU clock frequency 866 766 667 667 MHz

CPU_3X2X_621_MAX

Maximum CPU_3X clock frequency 433 383 333 333 MHz

CPU_2X_621_MAX

Maximum CPU_2X clock frequency 288 255 222 222 MHz

CPU_1X_621_MAX

Maximum CPU_1X clock frequency 144 127 111 111 MHz

CPU_6X4X_421_MAX

(1)

4:2:1

Maximum CPU clock frequency 710 600 533 533 MHz

CPU_3X2X_421_MAX

Maximum CPU_3X clock frequency 355 300 267 267 MHz

CPU_2X_421_MAX

Maximum CPU_2X clock frequency 355 300 267 267 MHz

CPU_1X_421_MAX

Maximum CPU_1X clock frequency 178 150 133 133 MHz

Notes:

1. The maximum frequency during BootROM execution is 500 MHz across all speed specifications.

Table 18: PS DDR Clock Domains Performance

(1)

Symbol Description

Speed Grade

Units

-3 -2 -1C/-1I/-1LI -1Q

DDR3_MAX

Maximum DDR3 interface performance 1066 1066 1066 1066 Mb/s

DDR3L_MAX

Maximum DDR3L interface performance 1066 1066 1066 1066 Mb/s

DDR2_MAX

Maximum DDR2 interface performance 800 800 800 800 Mb/s

LPDDR2_MAX

Maximum LPDDR2 interface performance 800 800 800 800 Mb/s

DDRCLK_2XMAX

Maximum DDR_2X clock frequency 444 408 355 355 MHz

Notes:

1. All performance numbers apply to both internal and external V

REF

configurations.

Table 19: PS-PL Interface Performance

Symbol Description Min Max Units

EMIOGEMCLK

EMIO gigabit Ethernet controller maximum frequency – 125 MHz

EMIOSDCLK

EMIO SD controller maximum frequency – 25 MHz

EMIOSPICLK

EMIO SPI controller maximum frequency – 25 MHz

EMIOJTAGCLK

EMIO JTAG controller maximum frequency – 20 MHz

EMIOTRACECLK

EMIO trace controller maximum frequency – 125 MHz

FTMCLK

Fabric trace monitor maximum frequency – 125 MHz

EMIODMACLK

DMA maximum frequency – 100 MHz

AXI_MAX

Maximum AXI interface performance – 250 MHz

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