Intel X557-AT/AT2/AT4 10GBE PHY 数据手册：低功耗高性能网络解决方案

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"x557-at-at2-at4-10gbe-phy-datasheet.pdf" 本文档是Intel® X557-AT/AT2/AT4 10 Gigabit Ethernet PHY (X557)的数据表，这是一种单端口（AT）、双端口（AT2）和四端口（AT4）的28纳米CMOS三速PHY，专为需要10GBASE-T功能的网络接口卡（NICs）、交换机和主板上局域网（LOM）应用提供低功耗解决方案。 Intel X557的主要特性包括： 1. **10GBASE-T性能**：该PHY能够在保持低功耗和低延迟的同时，支持最差情况下的通道。它能兼容不同类型的以太网电缆： - 支持100米增强型CAT6（CAT6A和CAT7） - 支持55米CAT6，以及在最佳条件下使用CAT5e 2. **内置热管理功能**：允许在热约束环境中部署。包含一个板载热传感器，具有报警和警告阈值。未来版本的数据表将提供更多关于此功能的详细信息。 3. **封装设计**：采用19x19mm（单/双端口）或25x25mm（四端口）的翻转芯片BGA封装，这种设计成本低、散热好，并且与大规模PCB制造兼容。特点包括1毫米球间距和低热阻（θjc）。 4. **协议兼容性**：符合IEEE 802.3an-2008标准的自动协商，确保与现有以太网基础设施的互操作性。 5. **外部SPI闪存接口**：允许存储配置信息和其他非易失性数据。 6. **高性能接口**：支持全KR（带自动协商）/XFI/SGMII/F并带有AC-JTAG，确保在各种互连场景下无故障运行。 7. **环回功能**：该PHY还提供了环回功能，这在调试和测试网络设备时非常有用，可以检查链路的正确性。 Intel X557的设计考虑了功耗优化、散热管理和广泛的接口兼容性，使其成为10GBASE-T应用的理想选择。它适用于需要高带宽和可靠性的数据中心、企业网络和服务器平台，同时它的低功耗特性也使其适用于移动和嵌入式系统。此外，其紧凑的封装尺寸和灵活的热管理方案使得集成到各种硬件设计中变得简单。

Intel

X557-AT/AT2/AT4 10 GbE PHY Datasheet—Hardware Interfaces (X557-AT and X557-

AT2)

Table 2-3 shows the management interface frame format (802.3-2005 45.3). The fields are described in

the sections that follow.

Table 2-3 MDIO Frame Format

Idle (idle condition):

The idle condition on the management interface is a high-impedance state. All tri-state drivers are

disabled and the pull-up resistor(s) on the MDIO bus will pull the MDIO line to a one.

PRE (preamble):

Normal operation — At the beginning of each transaction, the station management entity will send a

sequence of 32 contiguous ones on the MDIO data line, along with 32 corresponding cycles on the MDC

to provide the MMD with a pattern that it can use to establish synchronization. Each MMD will observe a

sequence of 32 contiguous one bits on MDIO with 32 corresponding cycles on MDC before it responds to

any transaction.

Preamble suppression — The MDIO interface can optionally disable preamble detection by setting the

MDIO Preamble Detection Disable bit in the Global General Provisioning 2: Address 1E.C441 register. In

this mode of operation, one or more preamble bit are required followed by the 0x0 start of frame ST

bits.

ST (start of frame):

The start of frame for indirect access cycles is indicated by the <00> pattern. This pattern assures a

transition from the default one and identifies the frame as an indirect access. Frames that contain the

ST=<01> pattern defined in Clause 22 will be ignored by the MMDs within the X557.

OP (operation code):

The operation code field indicates the type of transaction being performed by the frame. A <00>

pattern indicates that the frame payload contains the address of the register to access. A <01> pattern

indicates that the frame payload contains data to be written to the register whose address was provided

in the previous address frame. A <11> pattern indicates that the frame is read operation. A <10>

pattern indicates that the frame is a post-read increment address operation.

PHYAD (PHY address):

The PHY address is five bits, allowing for 32 unique PHY addresses, and hence up to 32 PHYs on an

MDIO bus. The address of the PHY is determined from ADDR[4:0] for the X557-AT and ADDR[4:1] for

the X557-AT2 pins. The first PHY address bit to be transmitted and received is the MSB of the address.

The station management entity must have a priori knowledge of the appropriate PHY address for each

PHY to which it is attached, whether connected to a single PHY or to multiple PHYs.

Frame PRE ST OP PHYAD MMDAD TA Data Idle

Address 1...1 00 00 PPPPP EEEEE 10 AAAAAAAAAAAAAAAA Z

Write 1...1 00 01 PPPPP EEEEE 10 DDDDDDDDDDDDDDDD Z

Read 1...1 00 11 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z

Post-read

increment

address

1...1 00 10 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z

Hardware Interfaces (X557-AT and X557-AT2)—Intel

X557-AT/AT2/AT4 10 GbE PHY

Datasheet

MMDAD (MMD address):

The MMD address is five bits, allowing for 32 unique MMDs per PHY. The first MMD address bit

transmitted and received is the MSB of the address.

In addition the X557 supports a broadcast mode when the PHYAD is 0x00. Only the write and load

address opcodes are supported in broadcast mode. Read and post-read increment opcodes are ignored

in broadcast mode. This mode of operation can be enabled via the MDIO Broadcast Mode Enable bits in

the Global General Provisioning 2: Address 1E.C441 register.

TA (turnaround):

The turnaround time is a 2-bit time spacing between the MMD address field and the data field of a

management frame to avoid contention during a read transaction. For a read or post-read increment

address transaction, both the STA and the MMD remain in a high-impedance state for the first bit time

of the turnaround. The MMD then drives a zero bit during the second bit time of the turnaround of a

read or post-read increment address transaction. During a write or address transaction, the STA

transmits a one for the first bit time of the turnaround and a zero for the second bit time of the

turnaround. This behavior is shown in

Figure 2-1 MDIO Bus Turn-around During Read Operations

Address / Data:

The address/data field is 16 bits. For an address cycle, it contains the address of the register to be

accessed on the next cycle. For the data cycle of a write frame, the field contains the data to be written

to the register. For a read or post-read increment address frame, the field contains the contents of the

For counters that are greater than 16-bits, the LSW must be read first, then the MSW must be read

immediately afterwards. When the LSW is read, the counter is cleared and the MSW is stored in a

shadow register. Reading the MSW actually reads the shadow register.

Optionally the host may read the MSW first, then the LSW immediately afterwards by setting the MDIO

Read MSW First Enable bit in the Global General Provisioning 2: Address 1E.C441 register.

MDC*

MDIO Line

<MMD Address[0]><MMD Address[1]> <Z> <0> Data[15]

MDIO Driven by STA MDIO Driven by PHY MMD

Intel

X557-AT/AT2/AT4 10 GbE PHY Datasheet—Hardware Interfaces (X557-AT and X557-

AT2)

The SPI interface is a four wire, unidirectional, serial bus as shown in Figure 2-2. It is composed of a

serial clock output SCLK, a serial data output SOUT, a serial data input SIN, and a chip-select CE*. All

the signals are unidirectional.

Figure 2-2 SPI Interface Block Diagram

The X557 is set up to function as a Mode 0 (0,0) SPI device, which means that the clock defaults to zero

when not bursting. Data on this interface, for both SIN and SOUT, is always sourced on the falling edge

of SCLK, and sampled on the rising edge of SCLK.

The following figures show typical read, burst read, and write operations for the X557. In all of these

scenarios, the Non-volatile RAM (NVR) interface in the Global MMD is used to access the Flash.

Note: NVR used throughout this document is synonymous with Non-volatile Memory (NVM).

The NVR interface in the X557 is designed to be able to output any arbitrary opcode, followed by a

programmable zero to three address bytes, followed by a programmable zero to four data bytes. This

allows any variation of opcodes to be output to the attached Flash device. This interface also supports a

burst read and write mode, which keeps the CS* line pulled low to enable back-to-back reads and

writes. To support this, the NVR interface supports two 16-bit address registers and two 16-bit data

registers, which allows up to 4 data bytes in a burst over the SPI interface. In order to extend this to

longer bursts, the X557 halts the clock after the last bit in the data burst allowing the host processor to

load another block of data to / from the NVR interface. This is shown in Figure 2-3 through Figure 2-5

and enables the data burst to be extended by as many bytes as necessary, without outstripping the

MDIO’s I/O capabilities.

Figure 2-3 SPI Read

SCLK

SOUT

CE*

SIN

PHY

NVR

CS*

SCK

012345678

Mode 0

15 16 23 24 31 32 39 40 47 48 55 56 63

CS*

SCLK

SIN

SOUT

A2 A1 A0

n+1

n+3

Opcode = 0x3

000000

n+2

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