片上网络基础：权威教材解析

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"片上网络的经典教材" 片上网络（On-Chip Networks）是计算机架构领域中的一个重要概念，特别是在多核和芯片多处理器（Chip Multiprocessor，CMP）设计中不可或缺。随着半导体技术的发展，单个芯片上的计算单元数量不断增加，传统的总线结构已无法满足高带宽、低延迟的需求。因此，片上网络作为一种高效通信架构，被引入来解决这个问题。本书由权威人士Natalie Enright Jerger和Li-Shiuan Peh撰写，提供了对片上网络的深入理解和详细解析。它涵盖了片上网络的设计原则、路由算法、通信协议以及性能优化策略。在篇幅虽短但内容精炼的章节中，作者们探讨了如何通过片上网络有效地连接和管理芯片上的各个处理核心，以实现更高的并行性和系统性能。片上网络的关键特性包括网络拓扑（如环形、网格、树形等）、交换节点设计、流量控制机制以及错误检测与恢复策略。这些内容对于理解如何在有限的芯片空间内构建高效能、低能耗的并行计算系统至关重要。例如，书中可能详细讨论了虚拟通道技术，该技术允许在同一个物理通道上同时传输多个数据包，从而提高了网络的利用率和吞吐量。此外，书中的标签还提到了"教材"，表明这本书适合教学和自学。它不仅提供理论知识，还可能包含实际案例分析和设计实例，帮助读者将理论应用于实践。其他相关书籍，如《The Memory System》、《Fault Tolerant Computer Architecture》和《Transactional Memory》，则分别涉及内存系统、容错计算机架构和事务性内存，这些都是构建现代计算机系统时需要考虑的重要方面。片上网络的设计和优化对于实现高性能、低功耗的计算机架构具有重大意义。随着云计算和大数据中心的发展，仓库规模机器（Warehouse-Scale Machines）的设计变得越来越重要，而片上网络是这些大规模系统中不可或缺的组成部分。因此，理解并掌握片上网络的知识对于计算机硬件设计者和研究者来说至关重要。

2 CHAPTER 1. INTRODUCTION

Multi-core and many-core architectures will be commonplace in a variety of computing

domains. These architectures will enable increased levels of server consolidation in data centers

[68,143,13].Desktop applications,particularly graphics can leverage the multi-core wave [190,137].

High-bandwidth communication will be required for these throughput-oriented applications.Com-

munication latency can have a signiﬁcant impact on the performance of multi-threaded workloads;

synchronization between threads will require low-overhead communication in order to scale to a

large number of cores. In MPSoCs, leveraging an on-chip network can help enable design isolation:

MPSoCs utilize heterogeneous IP blocks

from a variety of vendors; with standard interfaces, these

blocks can communicate through an on-chip network in a plug-and-play fashion.

1.2 ON-CHIP VS. OFF-CHIP NETWORKS

While on-chip networks can leverage ideas from prior multi-chassis interconnection networks

used in supercomputers [72, 189, 4, 76], clusters of workstations [18] and Internet routers [44],

the design requirements facing on-chip networks differ starkly in magnitude; hence novel designs

are critically needed. Fortunately, by moving on-chip, the I/O bottlenecks that faced prior multi-

chassis interconnection networks are alleviated substantially: The abundant on-chip wiring supplies

bandwidth that is orders of magnitude higher than off-chip I/Os while obviating the inherent delay

overheads associated with off-chip I/O transmission.

On the other hand, a number of stringent technology constraints present challenges for

on-chip network designs. Speciﬁcally, on-chip networks targeting high-performance multi-core

processors must supply high bandwidth at ultra-low latencies, with a tight power envelope and

area budget. With multi-core and many-core chips, caches and interconnects compete with the

cores for the same chip real estate. Integrating a large number of components under tight area

and power constraints poses a signiﬁcant challenge for architects to create a balance between these

components. For instance, the Sun Niagara 2’s ﬂat 8 × 9 crossbar interconnecting all cores and the

memory controller has an area footprint close to that of a core. For the 16 cores in Sun’s Rock

architecture, if the same ﬂat crossbar architecture is used, it will require a 17 × 17 crossbar that will

take up at least 8x more area than the ﬁnal hierarchical crossbar design chosen: A 5x5 crossbar

connecting clusters of four cores each [204].

In order for widespread adoption of on-chip networks, the communication latency of a net-

work implementation must be competitive with crossbars. Furthermore, although on-chip networks

require much less power than buses and crossbars, they need to be carefully designed as on-chip

network power consumption can be high [211, 27]. For example, up to ∼ 30% of chip power is con-

sumed by Intel’s 80-core TeraFLOPS network [103, 207] and 36% by the RAW on-chip network

[202]. Therefore, it is essential that power constraints are evaluated as this ﬁeld matures.

IP blocks are intellectual property in the form of soft macros of reusable logic.

Also referred to as off-chip interconnection networks.

1.3. NETWORK BASICS: A QUICK PRIMER 3

1.3 NETWORK BASICS: A QUICK PRIMER

In the next few sections, we lay a foundation for terminology and topics covered within this book.

Subsequent chapterswill explore many ofthese areasinmoredepth as wellas state-of-the-art research

for different components of on-chip network design. Many fundamental concepts are applicable to

off-chip networks as well with different sets of design trade-offs and opportunities for innovation

in each domain.

Several acronyms have emerged as on-chip network research has gained momentum. Some

examples are NoC (network-on-chip), OCIN (on-chip interconnection network) and OCN (on-

NoC

OCIN

OCN

chip network). As there is no widely-agreed upon difference between them, throughout this book

we avoid the use of acronyms and generically refer to all kinds of on-chip networks.

1.3.1 EVOLUTION TO ON-CHIP NETWORKS

An on-chip network, as a subset of a broader class of interconnection networks, can be viewed

as a programmable system that facilitates the transporting of data between nodes

. An on-chip

network can be viewed as a system because it integrates many components including channels,

buffers, switches and control.

With a small number of nodes, dedicated ad hoc wiring can be used to interconnect them.

However,the use of dedicated wires is problematic as we increase the number of components on-chip:

The amount of wiring required to directly connect every component will become prohibitive.

Designs with low core counts can leverage buses and crossbars, which are considered the

simplest variants of on-chip networks. In both traditional multiprocessor systems and newer multi-

core architectures, bus-based systems scale only to a modest number of processors. This limited

scalability is because bus trafﬁc quickly reaches saturation as more cores are added to the bus, so it

is hard to attain high bandwidth. The power required to drive a long bus with many cores tapping

onto it is also exorbitant. In addition, a centralized arbiter adds arbitration latency as core counts

increase.To address these problems, sophisticated bus designs incorporate segmentation, distributed

arbitration, split transactions and increasingly resemble switched on-chip networks.

Crossbars address the bandwidth problem of buses, and have been used for on-chip inter-

connects for a small number of nodes. However, crossbars scale poorly for a large number of cores;

requiring a large area footprint and consuming high power. In response, hierarchical crossbars,where

cores are clustered into nodes and several levels of smaller crossbars provide the interconnection, are

used.These sophisticated crossbars resemble multi-hop on-chip networks where each hop comprises

small crossbars.

On-chip networks are an attractive alternative to buses and crossbars for several reasons. First

and foremost, networks represent a scalable solution to on-chip communication, due to their ability

to supply scalable bandwidth at low area and power overheads that correlate sub-linearly with the

number of nodes. Second, on-chip networks are very efﬁcient in their use of wiring, multiplexing

different communication ﬂows on the same links allowing for high bandwidth. Finally, on-chip

A node is any component that connects to the network: e.g core, cache, memory controller, etc.

4 CHAPTER 1. INTRODUCTION

networks with regular topologies have local, short interconnects that are ﬁxed in length and can be

optimized and built modularly using regular repetitive structures, easing the burden of veriﬁcation.

1.3.2 ON-CHIP NETWORK BUILDING BLOCKS

The design of an on-chip network can be broken down into its various building blocks: its topology,

routing, ﬂow control, router microarchitecture and design, and link architecture. The rest of this

lecture is organized along these building blocks and we will brieﬂy explain each in turn here.

Topology. An on-chip network is composed of channels and router nodes. The network

topology determines the physical layout and connections between nodes and channels in the network.

Routing.For a given topology,the routing algorithm determines the path through the network

that a message will take to reach its destination. A routing algorithm’s ability to balance trafﬁc (or

load) has a direct impact on the throughput and performance of the network.

Flow control. Flow control determines how resources are allocated to messages as they travel

through the network. The ﬂow control mechanism is responsible for allocating (and de-allocating)

buffers and channel bandwidth to waiting packets

. Resources can be allocated to packets in their

entirety (done in store-and-forward and virtual cut-through ﬂow control); however, this requires

very large buffer resources making it impractical on chip.Most commonly, on-chip networks handle

ﬂow control at the ﬂit level

. Buffers and channel bandwidth are allocated on the smaller granularity

of ﬂits rather than whole packets; as a result, routers can be designed with smaller buffers.

Router microarchitecture. A generic router microarchitecture is comprised of the following

components: input buffers, router state, routing logic, allocators, and a crossbar (or switch). Router

functionality is often pipelined to improve throughput. Delay through each router in the on-chip

network is the primary contributor to communication latency. As a result, signiﬁcant research effort

has been spent reducing router pipeline stages and improving throughput.

Link architecture.Thus far,all on-chip network prototypes have used conventional full-swing

logic and pipelined wires. Pipelined wires uses repeaters to improve signal reach. While full-swing

repeatered links dominate current designs, there are exciting ongoing research and opportunities for

alternative link architectures. We discuss this research in Chapter 7.

1.3.3 PERFORMANCE AND COST

As we discuss different on-chip design points and relevant research, it is important to consider both

the performance and the cost of the network. Performance is generally measured in terms of network

latency or accepted trafﬁc. For back-of-the-envelope performance calculations, zero-load latency is

zero-load

latency

often used, i.e. the latency experienced by a packet when there are no other packets in the network.

Zero-load latency provides a lower bound on average message latency. Zero-load latency is found by

taking the average distance (given in terms of network hops) a message will travel times the latency

to traverse a single hop.

A packet is a subdivision of a message.

A ﬂit is a ﬂow control unit, a subdivision of a packet.

1.4. COMMERCIAL ON-CHIP NETWORK CHIPS 5

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







Figure 1.1: Latency vs Throughput for an on-chip network.

In addition to providing ultra-low latency communication, network’s must also deliver high

throughput.Therefore, performance is also measured by its throughput. A high saturation through-

put indicates that the network can accept a large amount of trafﬁc before all packets experience very

saturation

throughput

high latencies, sustaining higher bandwidth. Figure 1.1 presents a latency versus throughput curve

for an on-chip network illustrating the zero-load latency and saturation throughput.

The two primary costs associated with an on-chip network are area and power. As mentioned,

many-core architectures operate under very tight power budgets.The impact of different designs on

power and area will be discussed throughout this book.

1.4 COMMERCIAL ON-CHIP NETWORK CHIPS

With on-chip networks being a nascent research area, there are only a handful of chips that have

been designed incorporating sophisticated on-chip networks [202, 187, 94, 190, 199, 184, 130, 154,

93, 212, 208]

. In this book, we select four commercial chips as case studies for illustrating the

diversity in on-chip network chip designs. A brief summary of the chips is given here, followed by a

discussion of their speciﬁc design choices in network interface design, topology, routing, ﬂow control

and router microarchitecture in subsequent chapters.

IBM Cell. The Cell architecture [94, 85] is a joint effort between IBM, Sony and Toshiba

to design a power-efﬁcient family of chips targeting game systems, but that are general enough

for other domains as well. Cell is a product that is in most game consoles in the market today.

It is a 90nm, 221mm

chip that can run at frequencies above 4GHz. It consists of one IBM 64-

This is a non-exhaustive list of academic and industrial chips, to the best of the authors’ knowledge.

6 CHAPTER 1. INTRODUCTION

bit Power Architecture core and eight Synergistic Processing Elements (SPEs) that are single-

instruction-multiple-data (SIMD)-based. These nine nodes are interconnected with an on-chip

Element Interconnect Bus (EIB) that overlays bus access semantics on four ring networks, with a

maximum bisection bandwidth of over 300GBytes/s

bisection

bandwidth

Intel TeraFLOPS. The TeraFLOPS processor [207, 208, 95] is a research prototype chip

that is targeted at exploring future processor designs with high core counts. It is a 65nm, 275mm

chip with 80 tiles running at a targeted frequency of 5GHz. Each tile has a processing engine (PE)

connected to an on-chip network router. The PE consists of two single-precision ﬂoating-point

multiply-accumulator (FPMAC) units; 3KB of single-cycle instruction memory (IMEM),and 2KB

of data memory (DMEM). The router interface block (RIB) interfaces the PE with the router, and

any PE can send or receive instruction and data packets to or from any other PE. Two FPMACs in

each PE providing 20 GigaFLOPS of aggregate performance, partnered with a maximum bisection

bandwidth of 320 GBytes/s in the on-chip network enable the chip to realize a sustained performance

of 10

ﬂoating-point operations per second (1.0 TeraFLOPS) while dissipating less than 100W.

Tilera TILE64 andTILE64Pro. The TILE64 and TILE64Pro architectures [25, 7, 212]are

products fromTilera targeted towards high-performance embedded applications such as networking

and real-time video processing. These chips support a shared memory space across the 64 tiles

(TILE64Pro has additional support for cache coherence termed Dynamic Distributed Cache), with

each tile consisting of L1 and L2 caches and a 3-issue VLIW processor core connected to the four

mesh networks. The TILE64 chip at 90nm, 750MHz, has 5MB of on-chip cache and on-chip

networks that provide a maximum bisection bandwidth of 2Tb/s with each tile dissipating less than

300mW.

ST Microelectronics STNoC.The STNoC [43, 42] is a prototype architecture and method-

ology targeted to replace the widely-used STBus in MPSoCs. It is targeted towards the unique

demands of MPSoCs on the on-chip network fabric: automated synthesis of network design, com-

patibility with heterogeneous, diverse IP blocks from other vendors and prior knowledge of trafﬁc

demands.It has been applied to the Morpheus chip targeting 90nm, with eight nodes on the on-chip

network connecting an ARM9 core, an array of ALUs, a reconﬁgurable array, embedded FPGA,

and memory controllers [124].

1.5 THIS BOOK

The book targets engineers and researchers familiar with many basic computer architecture concepts

who are interested in learning about on-chip networks.This work is designed to be a short synthesis

of the most critical concepts in on-chip network design. We envision this book as a resource for both

understanding on-chip network basics and for providing an overview of state-of-the-art research in

on-chip networks as of Summer 2009. We believe that an overview that teaches both fundamental

concepts and highlights state-of-the-art designs will be of great value to both graduate students and

Bisection bandwidth is the bandwidth across the cut down the middle of the network.

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