DS21348TN手册：3.3V E1/T1/J1线接口设备特性与功能详解

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DS21348TN是一款专为E1、T1和J1线路接口设计的全面解决方案，集成了高级功能，适用于长距离和短距离的通信线路。这款设备的核心特性包括： 1. **完整的E1、T1和J1线路接口单元（LIU）**：它作为一个单一的硬件平台，能够处理多种通信标准，提高了系统的灵活性和兼容性。 2. **支持多种传输模式**：无论是长途通信的E1标准（2.048 Mbps）还是T1标准（1.544 Mbps）的长距离或短距离连接，DS21348TN都能适应。 3. **可配置的接收侧终端匹配**：内置软件选择性接收侧终端匹配功能，可以适应75Ω、100Ω和120Ω的不同线路阻抗，以优化信号传输。 4. **低功耗设计**：采用3.3V电源，能有效降低能耗，适合对功耗敏感的应用场合。 5. **高精度时钟管理**：支持32位或128位无晶体振荡器Jitter Attenuator，仅需2.048 MHz主时钟即可工作，同时提供1.544 MHz选项用于T1模式。 6. **多种速率和同步支持**：提供16.384 MHz、8.192 MHz、4.096 MHz和2.048 MHz的时钟输出，可与恢复时钟同步。 7. **高级纠错编码**：支持AMI（阿梅里亚）、HDB3和B8ZS编码解码技术，确保数据在传输过程中的准确性和可靠性。 8. **灵活的工作模式**：具备可编程监控模式，允许接收器在不同状态下工作，提高系统监控能力。 9. **诊断功能**：包括环回测试、PRBS（循环冗余校验）模式生成和检测，以及接收错误输出，便于故障排查。 10. **In-Band Loop Code支持**：设备能生成和检测1到16位的In-Band Loop Code，包括CSU Loop Code，增强网络的连通性和错误检测。 11. **接口灵活性**：提供8位并行或串行接口，方便与其他设备进行连接和数据交换。 DS21348TN是一款功能强大且高度灵活的线路接口设备，适用于各种通信应用场景，通过其出色的性能和特性，为通信网络提供可靠的数据传输和高质量的信号处理。对于需要在不同通信标准和应用场景中部署的项目，这款芯片是理想的解决方案。同时，要注意查阅Maxim IC网站的官方文档，获取最新的设备修正信息（errata），确保设备运行的稳定性和兼容性。

DS21348/DS21Q348

13 of 76

DS21348T DS21348G

I/O

HARDWARE

MODE

17 E4 I/O LOOP1

18 G4 I/O MM0

19 F5 I/O MM1

20 G5 I VSM

21 F6 — VDD

22 G6 — VSS

23 E5 I/O RT1

24 E6 O PBEO

25 F7 O RCL

26 D6 I TEST

27 D5 I RTIP

28 D7 I RRING

29 C6 I

HRST

30 C7 I MCLK

31 B6 O BPCLK

32 B7 I BIS0

33 A7 I BIS1

34 C5 O TTIP

35 B5 — VSS

36 A6 — VDD

37 B4 O TRING

38 C4 O RPOS

39 A4 O RNEG

40 B3 O RCLK

41 A3 I TPOS

42 B2 I TNEG

43 A2 I TCLK

44 A1 I RT0

DS21348/DS21Q348

14 of 76

2.1 Pin Descriptions

Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,

DS21348T Pin Numbering)

NAME PIN I/O FUNCTION

A0 to A4 11 to 7 I

Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =

1), serves as the address bus. In multiplexed bus operation (BIS1 =

0, BIS0 = 0), these pins are not used and should be tied low.

ALE (AS) 4 I

Address Latch Enable (Address Strobe). When using the parallel

port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to

demultiplex the bus on a positive-going edge. In nonmultiplexed bus

mode (BIS0 = 1), should be tied low.

BIS0/BIS1 32/33 I

Bus Interface Select Bits 0 and 1. Used to select bus interface

option. See Table 2-1

for details.

BPCLK 31 O

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz

output.

1 I

Chip Select, Active Low. This active-low signal must be low to

read or write to the device.

D0/AD0 to

D7/AD7

19 to 12 I/O

Data Bus/Address/Data Bus. In nonmultiplexed bus operation

(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus

operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed

address/data bus.

HRST

29 I

Hardware Reset, Active Low. Bringing HRST low resets the

DS21348, setting all control bits to their default state of all zeros.

INT

23 O

Interrupt, Active Low. Flags host controller during conditions and

change of conditions defined in the Status Register. Active low,

open drain output.

MCLK 30 I

Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz

clock source is optional.

N/A — I Not Assigned. Should be tied low.

PBEO 24 O

PRBS Bit Error Output. The receiver will constantly search for a

-1 or a 2

-1 PRBS depending on the ETS bit setting (CCR1.7).

Remains high if out of synchronization with the PRBS pattern. Goes

low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization will cause a positive going

pulse (with same period as E1 or T1 clock) synchronous with

RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to a logic 1.

DS21348/DS21Q348

15 of 76

NAME PIN I/O FUNCTION

PBTS 44 I

Parallel Bus Type Select. When using the parallel port (BIS1 = 0),

set high to select Motorola bus timing, set low to select Intel bus

timing. This pin controls the function of the RD (DS), ALE (AS),

and WR (R/W) pins. If PBTS = 1 and BIS1 = 0, then these pins

assume the Motorola function listed in parentheses (). In serial port

mode, this pin should be tied low.

RCLK 40 O

Receive Clock. Buffered recovered clock from the line.

Synchronous to MCLK in absence of signal at RTIP and RRING.

RD (DS)

2 I

Read Input (Data Strobe), Active Low. DS is active low when in

nonmultiplexed, Motorola mode. See the bus timing diagrams in

Section 11.

RCL/

LOTC

25 O

Receive Carrier Loss/Loss of Transmit Clock. An output which

will toggle high during a receive carrier loss (CCR2.7 = 0) or will

toggle high if the TCLK pin has not been toggled for 5 µsec ± 2

µsec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware

mode.

RNEG 39 O

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)

or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out

of the line interface. Set NRZE (CCR1.6) to a one for NRZ

applications. In NRZ mode, data will be output on RPOS while a

received error will cause a positive-going pulse synchronous with

RCLK at RNEG. See Section 6.4 for details.

RPOS 38 O

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or

the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the

line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In

NRZ mode, data will be output on RPOS while a received error will

cause a positive-going pulse synchronous with RCLK at RNEG. See

Section 6.4 for details.

RTIP/

RRING

27/28 I

Receive Tip and Ring. Analog inputs for clock recovery circuitry.

These pins connect via a 1:1 transformer to the line. See Section 5

for details.

TCLK 43 I

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to

clock data through the transmit side formatter. Can be sourced

internally by MCLK or RCLK. See Common Control Register 1 and

Figure 1-3.

TEST 26 I

Tri-State Control. Set high to tri-state all outputs and I/O pins

(including the parallel control port). Set low for normal operation.

Useful in board level testing.

TNEG 42 I

Transmit Negative Data. Sampled on the falling edge (CCR2.1 =

0) or the rising edge (CCR2.1 = 1) of TCLK for data to be

transmitted out onto the line.

TPOS 41 I

Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)

or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted

out onto the line.

DS21348/DS21Q348

16 of 76

NAME PIN I/O FUNCTION

TTIP/

TRING

34/37 O

Transmit Tip and Ring [TTIP AND TRING]. Analog line driver

outputs. These pins connect via a step-up transformer to the line. See

Section 5

for details.

VDD 21/36 — Positive Supply. 3.3V ±5%

VSM 20 I Voltage Supply Mode. Should be low for 3.3V operation.

VSS 22/35 —

Signal Ground

WR (R/W)

3 I

Write Input (Read/Write), Active Low. See the bus timing

diagrams in Section 11.

Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,

DS21348T Pin Numbering)

NAME PIN I/O FUNCTION

BIS0/BIS1 32/33 I

Bus Interface Select Bits 0 and 1. Used to select bus interface

option. See Table 2-1 for details.

BPCLK 31 O

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz

output.

1 I

Chip Select, Active Low. Active-low signal must be low to read or

write to the device.

HRST

29 I

Hardware Reset, Active Low. Bringing HRST low will reset the

DS21348 setting all control bits to their default state of all zeros.

ICES 8 I

Input Clock Edge Select. Selects whether the serial port data input

(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of

SCLK.

INT

23 O

Interrupt, Active Low. Flags host controller during conditions and

change of conditions defined in the Status Register. Active-low,

open-drain output.

MCLK 30 I

Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz

clock source is optional.

NA — I Not Assigned. Should be tied low.

OCES 9 I

Output Clock Edge Select. Selects whether the serial port data

output (SDO) is valid on the rising (OCES = 1) or falling edge

(OCES = 0) of SCLK.

PBEO 24 O

PRBS Bit Error Output. The receiver will constantly search for a

-1 or a 2

-1 PRBS depending on the ETS bit setting (CCR1.7).

Remains high if out of synchronization with the PRBS pattern. Goes

low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization will cause a positive going

pulse (with same period as E1 or T1 clock) synchronous with

RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to a logic 1.

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