W25Q128FV：小巧高效128M位串行闪存，支持SPI/QPI

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W25Q128FV是一款高性能的128M位（128兆比特）串行闪存内存，专为系统设计者在空间有限、引脚和功耗需求严格的场景下提供存储解决方案。这款闪存具有灵活性和卓越性能，适用于多种应用，如代码阴影到RAM、直接从双/四线串行接口（DQSPI或QPI）执行代码，以及存储语音、文本和数据。该系列的特点包括其单电源工作模式，可以在2.7V至3.6V电压范围内运行，同时保持低功耗，活动状态下的电流消耗仅为4mA，而在休眠状态下仅为1μA，非常适合电池供电设备。闪存提供了多种封装选项，如SOIC/VSOP208-mil（6mm x 8mm）、WSON6x5-mm/8x6-mm、SOIC300-mil、TFBGA8x6-mm（5x5或6x4球栅阵列）以及PDIP300-mil，以满足不同尺寸和密度的需求。 W25Q128FV的引脚配置和功能详细描述了如下的关键特性： 1. 引脚配置：文档详细列出了各种封装的引脚布局，包括 ChipSelect（/CS）用于选择存储块，Serial Data Input/Output（DI, DO 和 IO0-IO3）用于数据传输，WriteProtect（/WP）用于保护闪存免受意外写入，HOLD（/HOLD）用于控制数据缓冲，以及Serial Clock（CLK）用于同步操作。Reset（/RESET）引脚用于进行复位操作。 2. 功能描述： - SPI/QPI操作：支持标准SPI、双线SPI（DQSPI）、四线SPI（QuadSPI）和QPI（快速并行接口）操作，分别对应不同的指令集，使得设备能够在不同的总线环境下高效工作。 - Hold Function：设备内置了保持功能，当需要暂时停止数据传输时，可以使用这个功能来暂停闪存内部的操作，从而保护数据一致性。 3. 版本信息：W25Q128FV的发布的日期是2012年10月1日，此文档是修订版D，说明它可能包含最新的改进和更新。这款闪存因其高效的性能、小巧的封装和广泛的兼容性，被广泛应用于嵌入式系统、微控制器和物联网设备中，为开发者提供了可靠的数据存储解决方案。理解并有效利用这些特性，能帮助设计师在设计紧凑型系统时优化存储资源的使用和功耗管理。

W25Q128FV

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6.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern, the W25Q128FV

provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

• Device resets when VCC is below threshold

• Time delay write disable after Power-up

• Write enable/disable instructions and automatic write disable after erase or program

• Software and Hardware (/WP pin) write protection using Status Registers

• Additional Individual Block/Sector Locks for array protection

• Write Protection using Power-down instruction

• Lock Down write protection for Status Register until the next power-up

• One Time Program (OTP) write protection for array and Security Registers using Status Register

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q128FV will maintain a reset condition while VCC is below the

threshold value of V

WI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds V

WI, all program and erase related instructions are further disabled for a time delay of tPUW. This

includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status

the VCC-min level and t

VSL time delay is reached, and it must also track the VCC supply level at power-

down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to

accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector

Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a

program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-

disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the

Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings

allow a portion or the entire memory array to be configured as read only. Used in conjunction with the

Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware

control. See Status Register section for further information. Additionally, the Power-down instruction offers

an extra level of write protection as all instructions are ignored except for the Release Power-down

instruction.

The W25Q128FV also provides another Write Protect method using the Individual Block Locks. Each

64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the

top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is

0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or

Program commands issued to the corresponding sector or block will be ignored. When the device is

powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from

Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector

or block.

The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When

WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of

the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

W25Q128FV

Publication Release Date: October 01, 2012

- 16 - Revision D

7. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for W25Q128FV. The Read Status Register-1/2/3

instructions can be used to provide status on the availability of the flash memory array, whether the device

is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,

Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write

Status Register instruction can be used to configure the device write protection features, Quad SPI setting,

Security Register OTP locks, Hold/Reset functions, output driver strength and power-up Address Mode.

Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits

(SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

7.1 Status Registers

Figure 4a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or

Erase/Program Security Register instruction. During this time the device will ignore further instructions

except for the Read Status Register and Erase/Program Suspend instruction (see t

W, tPP, tSE, tBE, and

CE in AC Characteristics). When the program, erase or write status/security register instruction has

completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write

disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase

Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and

S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status

W in AC characteristics). All, none or a portion of the memory array can be

protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected.

W25Q128FV

- 17 -

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect

either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array

as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in

conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once

CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For

instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when

CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please

refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1 SRP0 /WP

Status

Description

0 0 X

Software

Protection

/WP pin has no control. The Status register can be written to

after a Write Enable instruction, WEL=1. [Factory Default]

0 1 0

Hardware

Protected

When /WP pin is low the Status Register locked and cannot

be written to.

0 1 1

Hardware

Unprotected

When /WP pin is high the Status register is unlocked and can

be written to after a Write Enable instruction, WEL=1.

1 0 X

Power Supply

Lock-Down

Status Register is protected and cannot be written to again

until the next power-down, power-up cycle.

(1)

1 1 X

One Time

Program

(2)

Status Register is permanently protected and cannot be

written to.

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

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W25Q128FV：小巧高效128M位串行闪存，支持SPI/QPI

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