"ARM PL192中断控制器手册简介及获得中断服务地址方法"

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该文档是关于ARM PrimeCell™ Vectored Interrupt Controller (PL192)的技术参考手册。PL192是一个中断控制器，它提供了中断服务地址的获取方式，包括VIC端口和AHB端口两种。其中，硬件获取地址的方式更为快速。该手册的版权归ARM有限公司所有，版权年份为2002年。该手册旨在提供关于PL192中断控制器的详细技术资料和参考信息。在该手册中，ARM特别指出了对版权的保护，要求所有权利保留。ARM、ARM Powered logo、Thumb和StrongARM等名称都是ARM有限公司的注册商标。此外，该手册还介绍了对本文档所做的修改和更新。这些修改可能包括对文档内容进行了修订、添加和删除。ARM保留对手册内容进行修改的权利，以确保其始终提供最新的技术信息。 PL192中断控制器是一种用于处理中断的硬件设备，它能够有效地管理和分配系统中的中断资源。中断是计算机系统中的一个重要概念，用于处理外部事件或内部异常。当系统遇到一个中断事件时，中断控制器能够及时捕捉并通知处理器，从而提高系统的实时性和可靠性。 PL192中断控制器的最大特点是采用了向量化的中断服务方式。在传统的中断处理方式中，中断服务程序的入口地址是固定的，处理器只能通过跳转到固定地址的方式来调用中断服务程序。而采用向量化的中断服务方式，中断控制器可以根据中断类型的不同，将中断入口地址映射到不同的位置，从而实现灵活的中断处理。 PL192中断控制器支持两种方式获取中断服务地址。VIC端口是一种通过编程配置的方式，可以将中断服务地址直接写入VIC寄存器。而AHB端口是一种通过硬件连接的方式，中断服务地址被直接加载到处理器的程序计数器（PC）中。相比之下，AHB端口的方式更为快速，因为它减少了中断服务地址的访问时间。总之，PL192中断控制器是一种高效的中断管理设备，能够提供灵活的中断处理方式。本手册对PL192中断控制器的技术规格和使用方法进行了详细介绍，可供开发人员和系统设计者参考和使用。对于需要提高系统实时性和可靠性的应用场景，PL192中断控制器是一个非常有价值的硬件组件。

Introduction

1.1 About the ARM PrimeCell Vectored Interrupt Controller (PL192)

The PrimeCell Vectored Interrupt Controller (VIC) is an Advanced Microcontroller Bus

Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed,

tested, and licensed by ARM.

The PrimeCell VIC provides an interface to the interrupt system, and improves interrupt

latency in two ways:

• moves the interrupt controller to the AMBA AHB bus

• provides vectored interrupt support for all interrupt sources

• provides support for the ARM v6 processor VIC port, compatible with ARM11

and ARM1026EJ processors.

1.1.1 Features of the PrimeCell VIC

The PrimeCell VIC has the following features:

• compliance to the AMBA Specification (Rev 2.0) for easy integration into

System-on-Chip (SoC) implementation

• support for 32 vectored IRQ interrupts

• fixed hardware interrupt priority levels

• programmable interrupt priority levels

• hardware interrupt priority level masking

• programmable interrupt priority level masking

• IRQ and FIQ generation

• AHB mapped for faster interrupt response

• software interrupt generation

• test registers

• raw interrupt status

• interrupt request status

• privileged mode support for restricted access

• interrupt controller daisy chaining (supports PL190, PL192, and AMBA

Development Kit (ADK)) interrupt controller

• support for the ARM v6 processor VIC port in synchronous and asynchronous

mode, enabling faster interrupt servicing when connected to an ARM11 or

ARM1026EJ processor.

Functional Overview

2.1 PrimeCell VIC overview

The PrimeCell VIC provides a software interface to the interrupt system. In a system

with an interrupt controller, software must determine the source that is requesting

service and where its service routine is loaded. A VIC does both of these in hardware.

It supplies the starting address (or vector address) of the service routine corresponding

to the highest priority requesting interrupt source.

In an ARM processor based system, two levels of interrupt are available:

• Fast Interrupt Request (FIQ) for fast, low latency interrupt handling

• Interrupt Request (IRQ) for more general interrupts.

Only a single FIQ source at a time is generally used in a system, to provide a true

low-latency interrupt. This has the following benefits:

• You can execute the interrupt service routine directly without determining the

source of the interrupt.

• Interrupt latency is reduced. You can use the banked registers available for FIQ

interrupts more efficiently, because a context save is not required.

The FIQ interrupt has the highest priority, followed by interrupt vector 0-31, and the

daisy-chained interrupt. The priority of each of the vectored interrupts is programmable,

enabling the order the interrupts are serviced in to be dynamically changed. This is done

by programming the values in the vector priority registers. If multiple interrupts are set

to the same programmed priority level, the fixed hardware priority levels are used to

determine the order the interrupts on that level are serviced. This is also applicable when

the priority registers are not programmed. Interrupt 0 has the highest hardware priority

level, and the daisy-chained interrupt has the lowest. The software can control each

request line to generate software interrupts.

The interrupt inputs must be level sensitive, active HIGH, and held asserted until the

interrupt is cleared in the peripheral by the interrupt service routine. Edge-triggered

interrupts are not compatible.

Note

The PrimeCell VIC does not handle interrupt sources with transient behavior. For

example, an interrupt is asserted and then deasserted before software can clear the

interrupt source. In this case, the CPU acknowledges the interrupt and obtains the

vectored address for the interrupt from the VIC, assuming that no other interrupt has

occurred to overwrite the vectored address. However, when a transient interrupt occurs,

the priority logic of the VIC is not set and lower priority interrupts are able to interrupt

the transient interrupt service routine, assuming interrupt nesting is allowed.

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