PCB仿真设置详解:PCI与PCIE硬件与软件配置指南

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在《EDA工具手册》中,"仿真设置-深入PCI与PCIE:硬件篇和软件篇"章节是关于电子设计自动化(EDA)软件——Cadence Allegro SPB V15.2的详细介绍。该部分着重于硬件和软件层面的PCB(Printed Circuit Board,印刷电路板)仿真设置,这是设计流程中的关键环节。 首先,章节从打开BRD(Board Description)文件开始,介绍了如何通过Cadence Product Choices界面启动Allegro PCB SI 630(SPECCTRAQuest),这是Cadence设计环境中的核心工具之一。用户需要通过File>Open命令,通过浏览器找到待仿真的PCB设计文件,这个过程确保了设计的正确导入和后续仿真工作的准确性。 仿真设置涉及的具体内容包括: 1. 硬件参数设置:在开始仿真前,必须对PCB的关键参数进行配置,这些可能包括但不限于电源电压、信号频率、线路阻抗等,以保证仿真结果的准确性和可靠性。 2. 库管理:Cadence库管理是设计过程中不可或缺的部分,包括原理图库(ConceptHDL)、PCB库和仿真库。3.2节详细解释了库的结构,如原理图库用于存放元器件模型,PCB库包含设计规则和封装,而仿真库则支持高速电路仿真所需的电路模型。 3. 公司设计规范:章节还涵盖了公司的特定PCB设计规范,以确保设计符合公司的标准和行业最佳实践,例如信号完整性(SI)和噪声免疫性。 4. 高速仿真:这部分讲解了如何使用Allegro SPB V15.2的PCBSI和SigXplorer进行高速信号行为仿真,这对于评估设计在实际工作频率下的性能至关重要。 5. 约束管理器:在原理图、PCB设计和仿真阶段,约束管理器被用来设定设计约束,如时序、功率、电磁兼容(EMC)要求,确保设计满足预设目标。 6. 自动布线:Allegro SPB V15.2的PCBRouter功能也在手册中有所介绍,它自动化了PCB布局布线的过程,提高了设计效率。 该章节内容详尽,旨在使读者能够掌握Cadence Allegro工具的基础操作,包括原理图设计、PCB布局、高速仿真以及约束和自动布线的使用,为实际的硬件设计提供坚实的理论和实践基础。通过阅读和实践,新进员工可以迅速融入到公司的EDA设计流程中。
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OBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 1.2. PCI EXPRESS LINK......................................................................................................... 39 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 1.3.1. Root Complex........................................................................................................ 41 1.3.2. Endpoints .............................................................................................................. 42 1.3.3. Switch.................................................................................................................... 45 1.3.4. Root Complex Event Collector.............................................................................. 46 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 46 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 47 1.5.1. Transaction Layer................................................................................................. 48 1.5.2. Data Link Layer .................................................................................................... 48 1.5.3. Physical Layer ...................................................................................................... 49 1.5.4. Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 53 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54 2.1.2. Packet Format Overview ...................................................................................... 56 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 58 2.2.1. Common Packet Header Fields ............................................................................ 58 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.3. TLP Digest Rules .................................................................................................. 65 2.2.4. Routing and Addressing Rules .............................................................................. 65 2.2.5. First/Last DW Byte Enables Rules........................................................................ 69 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules......................................................................................... 83 2.2.9. Completion Rules.................................................................................................. 97 2.2.10. TLP Prefix Rules ................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 104